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21. 发明申请

US20130228735A1 INTERFACIAL OXIDE USED AS SWITCHING LAYER IN A NONVOLATILE RESISTIVE MEMORY ELEMENT 有权
标题翻译：在非易失性存储元件中用作切换层的界面氧化物
公开(公告)号：US20130228735A1
公开(公告)日：2013-09-05
申请号：US13409436
申请日：2012-03-01
申请人： Randall Higuchi , Tony P. Chiang , Ryan Clarke , Vidyut Gopal , Imran Hashim , Robert Huertas , Yun Wang
发明人： Randall Higuchi , Tony P. Chiang , Ryan Clarke , Vidyut Gopal , Imran Hashim , Robert Huertas , Yun Wang
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2463 , H01L45/10 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments. The switching performance of a resistive memory device based on such an interfacial oxide layer is equivalent or superior to the performance of a conventional resistive memory element.
摘要翻译：非易失性电阻性存储元件包括由界面氧化物层形成的主体氧化物。界面氧化物层通过原位或沉积后表面氧化处理形成在沉积电极层的表面上。基于这样的界面氧化物层的电阻式存储器件的开关性能等同于或优于常规电阻式存储元件的性能。

22. 发明申请

US20130214232A1 NONVOLATILE MEMORY DEVICE USING A VARISTOR AS A CURRENT LIMITER ELEMENT 有权
标题翻译：使用VARISTOR作为当前限制元素的非易失性存储器件
公开(公告)号：US20130214232A1
公开(公告)日：2013-08-22
申请号：US13399815
申请日：2012-02-17
申请人： Mihir Tendulkar , Imran Hashim , Yun Wang
发明人： Mihir Tendulkar , Imran Hashim , Yun Wang
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1616
摘要： Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：本发明的实施例包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加设置在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。限流部件的电气特性被配置为在逻辑状态编程步骤期间通过在非易失性存储器件的电阻式开关存储器元件中添加固定串联电阻来降低通过可变电阻层的电流。在一些实施例中，限流部件包括变阻器，其是设置在非易失性电阻式开关存储器件中的电阻式开关存储器元件内的限流材料。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

23. 发明申请

US20130187110A1 NONVOLATILE MEMORY DEVICE USING A TUNNEL OXIDE AS A CURRENT LIMITER ELEMENT 有权
标题翻译：使用隧道氧化物作为电流限制元件的非易失性存储器件
公开(公告)号：US20130187110A1
公开(公告)日：2013-07-25
申请号：US13354006
申请日：2012-01-19
申请人： Mihir Tendulkar , Imran Hashim , Yun Wang
发明人： Mihir Tendulkar , Imran Hashim , Yun Wang
IPC分类号： H01L45/00 , H01L21/02 , B82Y99/00
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2463 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.
摘要翻译：本发明的实施例通常包括形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件的添加而具有改进的器件切换性能和寿命的电阻式开关存储元件。限流部件的电气特性被配置为在逻辑状态编程步骤期间通过在非易失性存储器件的电阻式开关存储器元件中添加固定串联电阻来降低通过可变电阻层的电流。在一个实施例中，限流部件包括隧道氧化物，隧道氧化物是设置在非易失性电阻式开关存储器件中的电阻式开关存储器元件内的限流材料。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

24. 发明申请

US20130107604A1 Method for Forming Resistive Switching Memory Elements with Improved Switching Behavior 有权
标题翻译：用于形成具有改进的开关行为的电阻式开关存储元件的方法
公开(公告)号：US20130107604A1
公开(公告)日：2013-05-02
申请号：US13281777
申请日：2011-10-26
申请人： Yun Wang , Tony Chiang , Imran Hashim , Vidyut Gopal
发明人： Yun Wang , Tony Chiang , Imran Hashim , Vidyut Gopal
IPC分类号： G11C11/00 , G01N27/00 , H01L21/8239
CPC分类号： H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/146 , H01L45/1641
摘要： Methods for producing RRAM resistive switching elements having optimal switching behavior include crystalline phase structural changes. Structural changes indicative of optimal switching behavior include hafnium oxide phases in an interfacial region between a resistive switching layer and an electrode.
摘要翻译：具有最佳切换行为的RRAM电阻式开关元件的制造方法包括晶相结构变化。指示最佳切换行为的结构变化包括在电阻式开关层和电极之间的界面区域中的氧化铪相。

25. 发明授权

US08383430B2 Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 失效
标题翻译：用于在半导体衬底上筛选多个样品的组合处理方法
公开(公告)号：US08383430B2
公开(公告)日：2013-02-26
申请号：US13399719
申请日：2012-02-17
申请人： Guarav Verma , Tony P. Chiang , Imran Hashim , Sandra G Malhotra , Prashant B Phatak , Kurt H Weiner
发明人： Guarav Verma , Tony P. Chiang , Imran Hashim , Sandra G Malhotra , Prashant B Phatak , Kurt H Weiner
IPC分类号： H01L21/00
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

26. 发明申请

US20130026438A1 CURRENT-LIMITING LAYER AND A CURRENT-REDUCING LAYER IN A MEMORY DEVICE 有权
标题翻译：电流限制层和存储器件中的电流减少层
公开(公告)号：US20130026438A1
公开(公告)日：2013-01-31
申请号：US13399530
申请日：2012-02-17
申请人： Yun Wang , Tony P. Chiang , Imran Hashim
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , G11C11/00 , G11C13/00 , G11C13/0007 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1641
摘要： A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.
摘要翻译：电流限制层和电流减少层被并入到电阻式开关存储器件中以形成存储器阵列。结合的限流层在电阻式开关存储器件的编程期间减少了电流尖峰的发生，并且并入的电流降低层使可流过电阻式开关存储器件的总体电流水平最小化。合并在一起的两个层次有助于提高设备性能和使用寿命。

27. 发明申请

US20120313069A1 WORK FUNCTION TAILORING FOR NONVOLATILE MEMORY APPLICATIONS 有权
标题翻译：用于非易失性存储器应用的工作功能定制
公开(公告)号：US20120313069A1
公开(公告)日：2012-12-13
申请号：US13156624
申请日：2011-06-09
申请人： Yun Wang , Tony Chiang , Imran Hashim
发明人： Yun Wang , Tony Chiang , Imran Hashim
IPC分类号： H01L47/00
CPC分类号： H01L45/1608 , H01L27/2463 , H01L45/04 , H01L45/065 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1633 , H01L45/1641
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

28. 发明申请

US20110151136A1 METHODS FOR DEPOSITING HIGH-K DIELECTRICS 有权
标题翻译：沉积高K电介质的方法
公开(公告)号：US20110151136A1
公开(公告)日：2011-06-23
申请号：US13039819
申请日：2011-03-03
申请人： Xiangxin Rui , Sunil Shanker , Sandra Malhotra , Imran Hashim , Edward Haywood
发明人： Xiangxin Rui , Sunil Shanker , Sandra Malhotra , Imran Hashim , Edward Haywood
IPC分类号： B05D3/06 , B05D3/02 , B05D5/12
CPC分类号： H01L21/3141 , C23C16/02 , C23C16/405 , H01L21/02186 , H01L21/02271 , H01L21/02315 , H01L21/31604 , H01L28/91
摘要： Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
摘要翻译：描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。

29. 发明申请

US20100001269A1 Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
标题翻译：在半导体基板上筛选多个样品的组合处理方法
公开(公告)号：US20100001269A1
公开(公告)日：2010-01-07
申请号：US12167118
申请日：2008-07-02
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： C23C16/00 , H01L21/66 , H01L23/58
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

30. 发明授权

US06500762B2 Method of depositing a copper seed layer which promotes improved feature surface coverage 有权
标题翻译：沉积铜种子层的方法，其促进改进的特征表面覆盖
公开(公告)号：US06500762B2
公开(公告)日：2002-12-31
申请号：US10056751
申请日：2002-01-24
申请人： Imran Hashim , Hong-Mei Zhang , John C. Forster
发明人： Imran Hashim , Hong-Mei Zhang , John C. Forster
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/2855 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： We have discovered a method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. We have demonstrated that it is possible to increase the copper seed layer coverage simultaneously at the bottom of a high aspect ratio contact via and on the walls of the via by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. An increase in the percentage of copper species which are ionized can be achieved using techniques known in the art, including but not limited to applicants' preferred technique, an inductively coupled RF ion metal plasma.
摘要翻译：我们已经发现了一种改进沉积在半导体特征表面上的铜籽晶层的台阶覆盖率的方法，该方法对于具有高纵横比的小尺寸特征特别有用。我们已经证明，可以通过增加作为离子的沉积铜物质的百分比，在高纵横比接触通孔和通孔的壁上同时增加铜种子层覆盖。获得铜种子层足够的阶梯覆盖所必需的物质电离的百分比是该特征的纵横比的函数。可以使用本领域已知的技术来实现电离的铜物质的百分比的增加，包括但不限于申请人的优选技术，电感耦合RF离子金属等离子体。

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