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21. 发明申请

US20100257415A1 INSTRUCTION-BASED PROGRAMMABLE MEMORY BUILT-IN SELF TEST CIRCUIT AND ADDRESS GENERATOR THEREOF 审中-公开
标题翻译：基于指令的可编程存储器内置自检程序及其地址发生器
公开(公告)号：US20100257415A1
公开(公告)日：2010-10-07
申请号：US12416646
申请日：2009-04-01
申请人： Chung-Fu Lin , Yeong-Jar Chang
发明人： Chung-Fu Lin , Yeong-Jar Chang
IPC分类号： G11C29/12 , G06F11/22 , G06F12/02
CPC分类号： G11C29/16 , G11C29/20 , G11C2029/0401
摘要： An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.
摘要翻译：提供了基于指令的可编程存储器内置自测（P-MBIST）电路及其地址发生器。 P-MBIST电路根据由外部自动测试设备（ATE）提供的紧凑测试指令的解码产生控制信号。地址生成器根据控制信号产生存储器地址。控制信号和存储器地址被发送到嵌入式存储器以执行MBIST。 P-MBIST电路和地址发生器的算法特定设计使得它们能够以全时钟速度支持多种测试算法，并占用更小的芯片面积。

22. 发明授权

US07564285B2 Controllable delay line and regulation compensation circuit thereof 有权
标题翻译：可控延迟线及其调节补偿电路
公开(公告)号：US07564285B2
公开(公告)日：2009-07-21
申请号：US11754783
申请日：2007-05-29
申请人： Chia-Wei Chang , Yeong-Jar Chang
发明人： Chia-Wei Chang , Yeong-Jar Chang
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.
摘要翻译：可控延迟线包括抗抖动单元，依赖电流源，第一电流镜，第二电流镜，调节电容器，补偿电容器和输出缓冲器单元。抗抖动单元接收第一偏置电压并且基于第一偏置电压产生第二偏置电压。当在可控延迟线中使用的电压源具有变化时，第二偏置电压随之变化。调节电容器用于减小电压源与第一电流源的节点电压之间的电压差的变化。补偿电容器用于减小输出缓冲器单元的输入信号对节点电压的转变的影响，以便降低输出缓冲器单元的输出信号的抖动量。

23. 发明申请

US20070040596A1 Opposite-phase scheme for peak current reduction 有权
标题翻译：峰值电流降低的相位方案
公开(公告)号：US20070040596A1
公开(公告)日：2007-02-22
申请号：US11285007
申请日：2005-11-23
申请人： Yow-Tyng Nieh , Sheng-Yu Hsu , Shih-Hsu Huang , Yeong-Jar Chang
发明人： Yow-Tyng Nieh , Sheng-Yu Hsu , Shih-Hsu Huang , Yeong-Jar Chang
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.
摘要翻译：我们提出了用于峰值电流降低的反相方案。基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段时钟源。因此，我们的方法可以有效地降低时钟树的峰值电流。该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

24. 发明授权

US10628627B2 Thermal estimation device and thermal estimation method 有权
公开(公告)号：US10628627B2
公开(公告)日：2020-04-21
申请号：US15857156
申请日：2017-12-28
申请人： Yeong-Jar Chang , Ya-Ting Shyu , Juin-Ming Lu , Yao-Hua Chen , Yen-Fu Chang , Jai-Ming Lin
发明人： Yeong-Jar Chang , Ya-Ting Shyu , Juin-Ming Lu , Yao-Hua Chen , Yen-Fu Chang , Jai-Ming Lin
IPC分类号： G06F30/398 , G06F30/30 , G06F30/367 , G06F119/06 , G06F119/08
CPC分类号： G06F30/398 , G06F30/30 , G06F30/367 , G06F2119/06 , G06F2119/08
摘要： An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.

25. 发明申请

US20090072869A1 SAMPLE AND HOLD CIRCUIT AND RELATED DATA SIGNAL DETECTING METHOD UTILIZING SAMPLE AND HOLD CIRCUIT 有权
标题翻译：采样和保持电路及相关数据信号检测方法利用样品和保持电路
公开(公告)号：US20090072869A1
公开(公告)日：2009-03-19
申请号：US11854560
申请日：2007-09-13
申请人： Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
发明人： Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
IPC分类号： G11C27/02
CPC分类号： G11C27/024 , G11C27/026
摘要： Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.
摘要翻译：公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

26. 发明授权

US07495479B1 Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit 有权
标题翻译：采样保持电路及相关数据信号检测方法利用采样保持电路
公开(公告)号：US07495479B1
公开(公告)日：2009-02-24
申请号：US11854560
申请日：2007-09-13
申请人： Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
发明人： Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
IPC分类号： H03K17/00
CPC分类号： G11C27/024 , G11C27/026
摘要： Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.
摘要翻译：公开了一种用于检测数据信号的参数的采样和保持电路，其包括：第一开关模块，其中所述采样和保持电路根据所述第一开关模块的导通或关断对所述数据信号进行采样; 耦合到所述第一开关模块的至少一个电容器; 耦合到所述电容器的第二开关模块; 可控参考电压源，用于提供第一参考电压，以根据控制信号经由第二开关模块对电容器充电/放电; 耦合到电容器的第一比较器，用于比较电容器上的电压降和第一参考电压以产生第一比较结果; 以及耦合到可控参考电压源和第一比较器的控制电路，用于根据比较结果产生控制信号。

27. 发明申请

US20060136793A1 Memory power models related to access information and methods thereof 有权
公开(公告)号：US20060136793A1
公开(公告)日：2006-06-22
申请号：US11116402
申请日：2005-04-28
申请人： Yaw-Feng Wang , Wen-Tsan Hsieh , Yi-Fang Chiu , Sheng-Yu Hsu , Yeong-Jar Chang
发明人： Yaw-Feng Wang , Wen-Tsan Hsieh , Yi-Fang Chiu , Sheng-Yu Hsu , Yeong-Jar Chang
IPC分类号： G11C29/00 , G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory device.

28. 发明授权

US08404501B2 Semiconductor package structure and manufacturing method thereof 有权
标题翻译：半导体封装结构及其制造方法
公开(公告)号：US08404501B2
公开(公告)日：2013-03-26
申请号：US12961512
申请日：2010-12-07
申请人： Po-Yao Huang , Chia-Yu Jin , Yeong-Jar Chang
发明人： Po-Yao Huang , Chia-Yu Jin , Yeong-Jar Chang
IPC分类号： H01L21/00 , H01L27/15 , H01L31/12 , H01L33/00
CPC分类号： G02B6/4292 , G02B6/4214 , G02B6/4249 , G02B6/4251 , G02B6/4253 , G02B6/4257 , G02B6/4274 , G02B6/428 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package structure includes a package substrate, at least a chip, solder balls, a light emitting/receiving device, a optical intermediary device and an optical transmission device. The package substrate has a first surface, a second surface, a circuit and solder ball pads, wherein each solder ball pad is electrically connected to the circuit. The chip is disposed on the first surface and electrically connected to the circuit. The solder balls are respectively disposed on the solder ball pads. The light emitting/receiving device is disposed on the package substrate and electrically connected to the circuit. The optical intermediary device is disposed above the light emitting/receiving device. The optical transmission device is inserted in the optical intermediary device, wherein a light emitting by the light emitting/receiving device is emitted to the optical transmission device via the optical intermediary device so that an optical signal is transmitted through the optical transmission device.
摘要翻译：半导体封装结构包括封装衬底，至少芯片，焊球，发光/接收器件，光中介器件和光传输器件。封装衬底具有第一表面，第二表面，电路和焊球垫，其中每个焊球焊盘电连接到电路。芯片设置在第一表面上并电连接到电路。焊球分别设置在焊球垫上。发光/接收装置设置在封装基板上并与电路电连接。光中继装置设置在发光/接收装置的上方。光传输装置被插入到光中继装置中，其中由发光/接收装置发射的光经由光中介装置发射到光传输装置，使得光信号通过光传输装置传输。

29. 发明授权

US07904874B2 Opposite-phase scheme for peak current reduction 有权
标题翻译：峰值电流降低的相位方案
公开(公告)号：US07904874B2
公开(公告)日：2011-03-08
申请号：US12010136
申请日：2008-01-22
申请人： Yow-Tyng Nieh , Sheng-Yu Hsu , Shih-Hsu Huang , Yeong-Jar Chang
发明人： Yow-Tyng Nieh , Sheng-Yu Hsu , Shih-Hsu Huang , Yeong-Jar Chang
IPC分类号： G06F17/50
CPC分类号： G06F1/10
摘要： We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.
摘要翻译：我们提出了用于峰值电流降低的反相方案。基本思想是将时钟树的每个级别的时钟缓冲区分为两组：一半时钟缓冲器与时钟源工作在相同的相位，而另一半的时钟缓冲器工作在相反的阶段时钟源。因此，我们的方法可以有效地降低时钟树的峰值电流。该方法使得相反方案能够与现代工业中常用的电子设计自动化（EDA）工具相结合。

30. 发明申请

US20090096439A1 BUILT-IN JITTER MEASUREMENT CIRCUIT 有权
标题翻译：内置抖动测量电路
公开(公告)号：US20090096439A1
公开(公告)日：2009-04-16
申请号：US11870113
申请日：2007-10-10
申请人： Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
发明人： Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
IPC分类号： G01R29/26 , G01R23/12
CPC分类号： G01R29/26 , G01R31/31709
摘要： A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.
摘要翻译：公开了抖动测量电路和校准抖动测量电路的方法。抖动测量电路包括同步双相检测器和判定电路。在测试模式中，获得由被测电路输出的时钟信号的抖动的概率分布函数（PDF）。在校准模式中，由被测电路中的自由振荡器外部产生或产生的随机时钟用于校准同步双相检测器。决定电路对由同步双相检测器检测的相位关系进行逻辑运算，数据锁存和计数，以获得相对于时钟信号的抖动的计数值和PDF。

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