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21. 发明授权

US08330209B2 HTO offset and BL trench process for memory device to improve device performance 有权
标题翻译： HTO偏移和BL沟槽工艺为存储器件提高器件性能
公开(公告)号：US08330209B2
公开(公告)日：2012-12-11
申请号：US13069710
申请日：2011-03-23
申请人： Ning Cheng , Huaqiang Wu , Hiro Kinoshita , Jihwan Choi
发明人： Ning Cheng , Huaqiang Wu , Hiro Kinoshita , Jihwan Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11565 , H01L27/11568 , H01L29/7923
摘要： Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
摘要翻译：提供具有增加的有效信道长度和/或改善的TPD特性的存储器件，以及制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。位线电介质可以延伸到半导体中。存储单元包含电荷捕获介质堆叠，多晶硅栅极，一对凹穴注入区域和一对位线。位线可以通过在较高能级和/或较高浓度的掺杂剂的注入工艺形成，而不会受到器件短沟道卷绕问题的影响，因为位线侧壁处的间隔物在较窄的植入区域中约束植入物。

22. 发明申请

US20120014693A1 Passive Optical Network with Adaptive Filters for Upstream Transmission Management 有权
标题翻译：用于上行传输管理的自适应滤波器的被动光网络
公开(公告)号：US20120014693A1
公开(公告)日：2012-01-19
申请号：US13179942
申请日：2011-07-11
申请人： Ning Cheng , Frank J. Effenberger , Guo Wei
发明人： Ning Cheng , Frank J. Effenberger , Guo Wei
IPC分类号： H04J14/02 , H04B10/08
CPC分类号： H04J14/0282
摘要： A wavelength division multiplexing passive optical network (WPON) comprising an optical line terminal (OLT) and a plurality of optical network units (ONUs) coupled to the OLT via a power optical splitter. The OLT is configured to monitor wavelengths in use by the ONUs and to divide upstream traffic from the ONUs into multiple channels using tunable filters. Also disclosed is an OLT for a PON, the OLT comprising a plurality of receivers and a plurality of tunable filters corresponding to each of the receivers. The OLT also comprises channel control logic coupled to the tunable filters, wherein the channel control logic is configured to detect a plurality of wavelengths in use for upstream traffic in the PON and to divide the upstream traffic into multiple channels using the tunable filters. Included is a method for managing upstream traffic in a PON, the method comprising monitoring, by a processor, wavelengths in use for upstream traffic in the PON. The method also comprises dividing the upstream traffic into multiple channels using tunable filters.
摘要翻译：一种波分复用无源光网络（WPON），包括通过功率分光器耦合到OLT的光线路终端（OLT）和多个光网络单元（ONU）。 OLT配置为监视ONU使用的波长，并使用可调滤波器将上行业务从ONU划分为多个通道。还公开了一种用于PON的OLT，OLT包括多个接收机和与每个接收机对应的多个可调滤波器。 OLT还包括耦合到可调谐滤波器的信道控制逻辑，其中信道控制逻辑被配置为检测用于PON中的上行业务的多个波长，并且使用可调滤波器将上行业务划分成多个信道。包括用于管理PON中的上行业务的方法，该方法包括由处理器监视用于PON中的上行业务的波长。该方法还包括使用可调滤波器将上游业务划分成多个信道。

23. 发明授权

US07906807B2 Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics 有权
标题翻译：在闪速存储器单元的位线结中使用聚合物间隔物和Si沟槽以改善TPD特性
公开(公告)号：US07906807B2
公开(公告)日：2011-03-15
申请号：US12827069
申请日：2010-06-30
申请人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , Kuo-Tung Chang , Huaqiang Wu
发明人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , Kuo-Tung Chang , Huaqiang Wu
IPC分类号： H01L29/92 , H01L29/76 , H01L21/336
CPC分类号： H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。位线电介质可以延伸到半导体中。存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

24. 发明申请

US20100264480A1 USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS 有权
标题翻译：在闪速存储器单元的位线结中使用聚合物间隔物和硅酸盐以提高TPD特性
公开(公告)号：US20100264480A1
公开(公告)日：2010-10-21
申请号：US12827069
申请日：2010-06-30
申请人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , K.T Chang , Huaqiang Wu
发明人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , K.T Chang , Huaqiang Wu
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。位线电介质可以延伸到半导体中。存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

25. 发明申请

US20100226649A1 Multi-Fiber Ten Gigabit Passive Optical network Optical Line Terminal for Optical Distribution Network Coexistence with Gigabit Passive Optical Network 失效
标题翻译：多光纤万兆无源光网络光网络终端，用于配光网络与千兆无源光网络共存
公开(公告)号：US20100226649A1
公开(公告)日：2010-09-09
申请号：US12709563
申请日：2010-02-22
申请人： Ning Cheng , Zhishan Feng , Frank Effenberger
发明人： Ning Cheng , Zhishan Feng , Frank Effenberger
IPC分类号： H04J14/02
CPC分类号： H04J14/0282 , H04J14/0209 , H04J14/0226 , H04J14/0238 , H04Q11/0067 , H04Q2011/0016 , H04Q2011/0079
摘要： An apparatus comprising a wavelength division multiplexing (WDM) coupler configured to couple an optical line terminal (OLT) comprising a transmitter and a receiver, wherein the WDM coupler is coupled to the transmitter via a first fiber and to the receiver via a second fiber. An apparatus comprising a WDM coupler for a passive optical network (PON) comprising a plurality of filters and a plurality of ports, wherein the WDM coupler comprises fewer filters than ports. A method comprising receiving a downstream optical signal intended for an optical network terminal (ONT) via a first fiber, and transmitting an upstream optical signal received from the ONT via a second fiber.
摘要翻译：一种包括配置成耦合包括发射机和接收机的光线路终端（OLT）的波分复用（WDM）耦合器的设备，其中所述WDM耦合器经由第一光纤耦合到所述发射机，并经由第二光纤耦合到所述接收机。一种包括用于无源光网络（PON）的WDM耦合器的装置，包括多个滤波器和多个端口，其中所述WDM耦合器包括比端口少的滤波器。一种方法，包括经由第一光纤接收用于光网络终端（ONT）的下行光信号，以及经由第二光纤发送从ONT接收的上行光信号。

26. 发明授权

US07705390B2 Dual bit flash memory devices and methods for fabricating the same 有权
标题翻译：双位闪存器件及其制造方法
公开(公告)号：US07705390B2
公开(公告)日：2010-04-27
申请号：US12054081
申请日：2008-03-24
申请人： Amol Ramesh Joshi , Ning Cheng , Minghao Shen
发明人： Amol Ramesh Joshi , Ning Cheng , Minghao Shen
IPC分类号： H01L21/76 , H01L21/792
CPC分类号： H01L29/66833 , H01L29/7923
摘要： Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.
摘要翻译：提供了制造双位闪存器件的方法。方法步骤包括形成覆盖衬底的电荷俘获层，并制造覆盖电荷俘获层的两个绝缘构件。提供了覆盖电荷捕获层和绝缘构件的侧壁的多晶硅层。侧壁间隔物形成在多晶硅层上并且围绕绝缘构件的侧壁。去除第一多晶硅层的一部分和电荷俘获层的第一部分。第一绝缘层共形沉积在绝缘构件和衬底上。在两个绝缘构件之间形成栅极间隔物并覆盖第一绝缘层。去除两个绝缘构件并蚀刻电荷捕获层以形成电荷存储节点。将杂质掺杂剂注入到衬底中以在衬底内形成杂质掺杂的位线区域。

27. 发明申请

US20100099249A1 SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK 有权
标题翻译：选择性硅胶形成使用耐蚀蚀回填
公开(公告)号：US20100099249A1
公开(公告)日：2010-04-22
申请号：US12644457
申请日：2009-12-22
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/285 , H01L21/3205
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

28. 发明授权

US07696038B1 Methods for fabricating flash memory devices 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07696038B1
公开(公告)日：2010-04-13
申请号：US11412365
申请日：2006-04-26
申请人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
发明人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , G11C16/3418 , G11C16/3427
摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.
摘要翻译：提供了制造闪速存储器件的方法。根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。第一杂质掺杂区域形成在沟槽下面的衬底内。

29. 发明授权

US07691751B2 Selective silicide formation using resist etchback 有权
标题翻译：使用抗蚀剂回蚀的选择性硅化物形成
公开(公告)号：US07691751B2
公开(公告)日：2010-04-06
申请号：US11924823
申请日：2007-10-26
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

30. 发明授权

US07507661B2 Method of forming narrowly spaced flash memory contact openings and lithography masks 有权
标题翻译：形成窄间隔闪存接触开口和光刻掩模的方法
公开(公告)号：US07507661B2
公开(公告)日：2009-03-24
申请号：US10916167
申请日：2004-08-11
申请人： Emmanuil H. Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
发明人： Emmanuil H. Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
IPC分类号： H01L21/44
CPC分类号： H01L27/11568 , G03F1/36 , H01L27/115 , Y10S438/942 , Y10S438/947
摘要： A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.
摘要翻译：提供了一种用于在光刻掩模上产生光学特征的方法，用于在半导体器件晶片上图案化一系列蚀刻掩模的开口，包括沿着第一方向在光刻掩模上彼此间隔开的一系列光学特征，其中各个光学特征具有沿着第一方向的第一掩模特征尺寸，其小于用于在蚀刻掩模中图案化的开口的期望的第一尺寸。

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