专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20080159047A1 Internal voltage generation circuit 有权
标题翻译：内部电压产生电路
公开(公告)号：US20080159047A1
公开(公告)日：2008-07-03
申请号：US11821600
申请日：2007-06-25
申请人： Shin Ho Chu
发明人： Shin Ho Chu
IPC分类号： G11C11/4193
CPC分类号： G11C5/14 , G05F1/465 , G11C5/144
摘要： Various examples of internal voltage generation circuit are provided. In one example, the internal voltage generation circuit includes a level control signal generator for generating a level control signal in response to a power down mode signal, which is activated synchronously with a clock enable signal, and a precharge flag signal, which is enabled when a precharge operation, is performed, and an internal voltage generator for generating an internal voltage in response to the level control signal and outputting it to an output node.
摘要翻译：提供内部电压产生电路的各种示例。在一个示例中，内部电压产生电路包括电平控制信号发生器，用于响应于与时钟使能信号同步激活的掉电模式信号和预充电标志信号产生电平控制信号，该预充电标志信号在执行预充电操作，以及内部电压发生器，用于响应于电平控制信号产生内部电压并将其输出到输出节点。

22. 发明申请

US20070285998A1 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US20070285998A1
公开(公告)日：2007-12-13
申请号：US11647483
申请日：2006-12-29
申请人： Sang Il Park , Shin Ho Chu
发明人： Sang Il Park , Shin Ho Chu
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , H01L25/0657 , H01L2224/48225 , H01L2224/48227 , H01L2225/06568 , H01L2924/15311
摘要： A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.
摘要翻译：响应于自刷新和有效信号，第一信号输入电路输出第一控制信号。第二信号输入电路响应于自刷新和有效信号而输出第二控制信号。电源电路响应于第一控制信号向输出端施加第一电源电压。升高的电压发生器通过泵浦第二电源电压产生升高的电压，并且响应于第一和第二控制信号将升高的电压施加到输出端子。

23. 发明授权

US08192082B2 Thermal data output circuit and multi chip package using the same 有权
标题翻译：热数据输出电路和多芯片封装使用相同
公开(公告)号：US08192082B2
公开(公告)日：2012-06-05
申请号：US12317218
申请日：2008-12-18
申请人： Ho Uk Song , Shin Ho Chu
发明人： Ho Uk Song , Shin Ho Chu
IPC分类号： G01K7/00
CPC分类号： G01K3/005
摘要： A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.
摘要翻译：提供温度数据输出电路，其能够输出当安装在多芯片封装上的至少一个半导体存储器芯片的内部温度超过预定温度时使能的温度信号。

24. 发明授权

US07688663B2 Anti-fuse repair control circuit and semiconductor device including DRAM having the same 失效
标题翻译：防熔丝修复控制电路和包括具有相同功能的DRAM的半导体器件
公开(公告)号：US07688663B2
公开(公告)日：2010-03-30
申请号：US11964155
申请日：2007-12-26
申请人： Shin Ho Chu , Sun Mo An
发明人： Shin Ho Chu , Sun Mo An
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C17/165 , G11C29/44 , G11C29/4401 , G11C29/785 , G11C2229/763
摘要： In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled.
摘要翻译：在反熔丝修复控制电路中，将半导体存储器件集成到多芯片封装中以进行抗熔丝修复。反熔丝修复控制电路包括数据掩模信号输入电路，单元地址使能单元，修复使能单元和修复单元。数据屏蔽信号输入电路在接收到用于反熔丝修复的测试控制信号时，接收并输出数据屏蔽信号。单元地址使能单元接收到反熔丝修复地址，以便在接收到从数据屏蔽信号输入电路输出的数据屏蔽信号时，使反熔丝单元的单元地址能够被修复。修复使能单元根据是否启用与单元地址对应的反熔丝单元，对单元地址进行编码并输出修复使能信号和驱动信号。当修复使能信号，地址和驱动信号被使能时，维修单元向反熔丝单元提供修复电压。

25. 发明授权

US07606105B2 Deep power down mode control circuit 有权
标题翻译：深度掉电模式控制电路
公开(公告)号：US07606105B2
公开(公告)日：2009-10-20
申请号：US11811863
申请日：2007-06-11
申请人： Shin Ho Chu
发明人： Shin Ho Chu
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C5/144
摘要： A deep power down mode control circuit is provided. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for delaying the deep power down signal for a predetermined delay time, and outputting the delayed signal.
摘要翻译：提供深度掉电模式控制电路。深度掉电模式控制电路包括深度掉电信号发生器，用于响应于突发命令信号和时钟使能信号输出深度掉电信号，以及深度掉电延迟控制器，用于将深度掉电信号延迟用于预定的延迟时间，并输出延迟的信号。

26. 发明授权

US07447097B2 TRAS adjusting circuit for self-refresh mode in a semiconductor device 有权
标题翻译：用于半导体器件中的自刷新模式的TRAS调整电路
公开(公告)号：US07447097B2
公开(公告)日：2008-11-04
申请号：US11648270
申请日：2006-12-29
申请人： Mi Hyun Hwang , Shin Ho Chu
发明人： Mi Hyun Hwang , Shin Ho Chu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4067
摘要： A tRAS adjusting circuit extends an active operation in a self-refresh operation. The tRAS adjusting circuit includes: a self-refresh sensing unit for receiving a self-refresh signal and a refresh signal and generating a sensing signal; a first extension unit for extending an enable interval of an active operation pulse; a second extension unit for extending an enable interval of an output signal of the first extension unit; a transfer unit for transferring either the output signal of the first extension unit or an output signal of the second extension unit as a tRAS signal according to an enable state of the sensing signal; and an active signal output unit for receiving the active operation pulse and tRAS signal and outputting an enable state of the active operation pulse as an active signal until the tRAS signal is disabled.
摘要翻译： tRAS调整电路在自刷新操作中扩展了活动操作。 tRAS调整电路包括：自刷新感测单元，用于接收自刷新信号和刷新信号并产生感测信号; 第一扩展单元，用于延长有效操作脉冲的使能间隔; 第二扩展单元，用于扩展第一扩展单元的输出信号的使能间隔; 传送单元，用于根据感测信号的使能状态将第一扩展单元的输出信号或第二扩展单元的输出信号作为tRAS信号传送; 以及有源信号输出单元，用于接收有源操作脉冲和tRAS信号，并且将有效操作脉冲的使能状态作为有效信号输出，直到tRAS信号被禁止为止。

27. 发明申请

US20080186798A1 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US20080186798A1
公开(公告)日：2008-08-07
申请号：US11819272
申请日：2007-06-26
申请人： Shin Ho Chu
发明人： Shin Ho Chu
IPC分类号： G11C8/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2225/0651 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package facilitates package connection due to different locations of input/output pads in each interlayer die depending on coding information in a multi-chip package. The semiconductor package includes many chips. Each of the chips includes: input/output pads configured to input and output data having a given bandwidth; a decoding pad configured to receive coding information; and a code control unit configured to decode the coding information and to enable an input/output pad positioned at a specific location among the input/output pads according to the decoding result.
摘要翻译：半导体封装根据多芯片封装中的编码信息，由于每个层间管芯中的输入/输出焊盘的不同位置而促进封装连接。半导体封装包括许多芯片。每个芯片包括：配置为输入和输出具有给定带宽的数据的输入/输出焊盘; 解码板，被配置为接收编码信息; 以及代码控制单元，被配置为根据解码结果对编码信息进行解码并使能位于输入/输出焊盘之间的特定位置的输入/输出焊盘。

28. 发明授权

US07368953B2 Buffer 失效
标题翻译：缓冲
公开(公告)号：US07368953B2
公开(公告)日：2008-05-06
申请号：US11275462
申请日：2006-01-06
申请人： Shin Ho Chu , Sun Mo An
发明人： Shin Ho Chu , Sun Mo An
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C11/406 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4076
摘要： A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from the buffer controller and a specific signal to output a control signal, and an internal clock generator controlled by the control signal from the logic circuit for buffering the external clock signal and generating internal clock signals.
摘要翻译：公开了缓冲器。缓冲器可以包括缓冲器控制器，用于缓冲与外部时钟信号同步的自动刷新操作中使能的刷新信号，用于对来自缓冲器控制器的输出信号进行逻辑运算的逻辑电路和特定信号输出控制信号和由来自逻辑电路的控制信号控制的内部时钟发生器，用于缓冲外部时钟信号并产生内部时钟信号。

29. 发明授权

US07126865B2 Memory device including parallel test circuit 有权
标题翻译：存储器件包括并联测试电路
公开(公告)号：US07126865B2
公开(公告)日：2006-10-24
申请号：US10879175
申请日：2004-06-30
申请人： Yun Seok Hong , Shin Ho Chu
发明人： Yun Seok Hong , Shin Ho Chu
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/48 , G11C2029/1804
摘要： A memory device including a parallel test circuit can overcome a channel deficiency phenomenon of test equipment by reducing the number of input/output pads. The memory device including a parallel test circuit comprises a burst length regulating block, a parallel test block, an output block and a plurality of input/output pads. The burst length regulating block sets a second burst length at a test mode which is longer than a first burst length at a normal mode. The parallel test block compresses data and tests the compressed data by a repair unit. The output block sequentially outputs data outputted from at least two or more parallel test blocks depending on the second burst length. The plurality of input/output pads externally output data outputted from the output block.
摘要翻译：包括并行测试电路的存储器件可以通过减少输入/输出焊盘的数量来克服测试设备的通道不足现象。包括并行测试电路的存储器件包括突发长度调节块，并行测试块，输出块和多个输入/输出焊盘。突发长度调节块在正常模式下在比第一突发长度长的测试模式下设置第二突发长度。并行测试块通过修复单元压缩数据并测试压缩数据。输出块根据第二突发长度顺序地输出从至少两个或更多个并行测试块输出的数据。多个输入/输出板从外部输出从输出块输出的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式