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21. 发明申请

US20080073688A1 One-Transistor Random Access Memory Technology Compatible with Metal Gate Process 有权
标题翻译：金属栅极工艺兼容的单晶硅随机存取技术
公开(公告)号：US20080073688A1
公开(公告)日：2008-03-27
申请号：US11836710
申请日：2007-08-09
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , Jian-Yu Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , Jian-Yu Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

22. 发明授权

US06794254B1 Embedded dual-port DRAM process 失效
标题翻译：嵌入式双端口DRAM工艺
公开(公告)号：US06794254B1
公开(公告)日：2004-09-21
申请号：US10438646
申请日：2003-05-15
申请人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
发明人： Kuo-Chyuan Tzeng , Ming-Hsiang Chiang , Wen-Chuan Chiang , Dennis J. Sinitsky
IPC分类号： H01L21336
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.
摘要翻译：实现了在集成电路器件中形成DRAM单元的新方法。该方法包括提供基底。在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。沟槽填充有第一介电层。所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。第二电介质层形成在衬底上并衬衬开放的沟槽。沉积覆盖第二介电层并完全填充开放沟槽的导电层。图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

23. 发明授权

US6143621A Capacitor circuit structure for determining overlay error 有权
标题翻译：用于确定覆盖误差的电容器电路结构
公开(公告)号：US6143621A
公开(公告)日：2000-11-07
申请号：US332382
申请日：1999-06-14
申请人： Kuo-Chyuan Tzeng , Wen-Jye Chung
发明人： Kuo-Chyuan Tzeng , Wen-Jye Chung
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L22/34 , Y10S438/975
摘要： A structure suitable for aligning two patterned conductive layers that are separated by a dielectric layer is described. Included in the lower pattern is a square and, as part of the upper pattern, four T-shaped capacitor electrodes are provided. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all electrodes. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.
摘要翻译：描述了适于对准由电介质层分离的两个图案化导电层的结构。包括在下图案中是正方形，并且作为上图案的一部分，提供四个T形电容器电极。后者被定位成使得当对准精确时，它们都与平方重叠相同的量。因此，在精确对准的条件下，在任何一个顶部电极和正方形之间测量的电容值对于所有电极将是相同的。然而，当发生不对准时，重叠的程度将改变，在正方形的一侧增加，而在相对侧减小。以这种方式，位于正方形的相对侧的电极之间的测量电容值的比较将指示是否以及在何种程度上发生未对准。

24. 发明申请

US20130037910A1 Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof 有权
标题翻译：解耦MIM电容器设计的插件及其制造方法
公开(公告)号：US20130037910A1
公开(公告)日：2013-02-14
申请号：US13209195
申请日：2011-08-12
申请人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
IPC分类号： H01L27/06 , H01L23/522 , H01L21/02
CPC分类号： H01L28/40 , H01L23/147 , H01L23/3114 , H01L23/49822 , H01L23/5223 , H01L24/83 , H01L27/06 , H01L27/0805 , H01L2224/131 , H01L2224/13144 , H01L2224/16235 , H01L2224/16238 , H01L2924/0002 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.
摘要翻译：公开了用于插入件的去耦金属绝缘体金属（MIM）电容器设计及其制造方法。在一个实施例中，形成去耦电容器的方法包括提供封装装置，以及在包装装置的至少两个金属化层中形成去耦MIM电容器。

25. 发明授权

US08012836B2 Semiconductor devices and methods for fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08012836B2
公开(公告)日：2011-09-06
申请号：US11528405
申请日：2006-09-28
申请人： Kuo-Chyuan Tzeng , Jian-Yu Shen , Kuo-Chi Tu , Kuo-Ching Huang , Chin-Yang Chang
发明人： Kuo-Chyuan Tzeng , Jian-Yu Shen , Kuo-Chi Tu , Kuo-Ching Huang , Chin-Yang Chang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894
摘要： Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.
摘要翻译：提供半导体器件及其制造方法。半导体器件的示例性实施例包括在其中形成有多个隔离结构的衬底，其在衬底上限定第一和第二区域。晶体管分别形成在第一和第二区域中的衬底的一部分上，其中第二区域中的晶体管仅在与衬底的漏极区相邻的衬底中仅形成一个凹坑掺杂区域。第一电介质层形成在衬底上，覆盖形成在第一和第二区域中的晶体管。通过第一介电层形成多个第一接触插塞，分别在第二区域中电连接晶体管的源极区域和漏极区域。在第一电介质层上形成第二电介质层，其中形成有电容器，其中电容器电连接第一接触插塞之一。

26. 发明授权

US07884408B2 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US07884408B2
公开(公告)日：2011-02-08
申请号：US11836710
申请日：2007-08-09
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , Jian-Yu Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , Jian-Yu Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

27. 发明申请

US20060017115A1 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US20060017115A1
公开(公告)日：2006-01-26
申请号：US10896491
申请日：2004-07-22
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

28. 发明授权

US06713406B1 Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices 失效
标题翻译：通过HDP（高密度等离子体）CVD（化学气相沉积）方法将电介质材料沉积到半导体衬底上而不损害FET有源器件的方法
公开(公告)号：US06713406B1
公开(公告)日：2004-03-30
申请号：US09809833
申请日：2001-03-19
申请人： Chu-Yun Fu , Kuo-Chyuan Tzeng
发明人： Chu-Yun Fu , Kuo-Chyuan Tzeng
IPC分类号： H01L21302
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02164 , H01L21/3105 , H01L21/31612 , H01L21/31625
摘要： Improved processes for depositing dielectric layers by HDP (High Density Plasma) CVD (Chemical Vapor Deposition) are described. One method controls the RF power applied to the side source RF power to be less than about 2500 Watts during dielectric deposition. A second method controls the thickness of the HDP-CVD deposited dielectric layer to be less than between about 2000 and 3000 Angstroms. These methods of HDP-CVD deposition of dielectric layers result in elimination or suppression of plasma induced damage to MOSFET devices and improved gate oxide integrity of MOSFET devices following deposition of dielectric layers by HDP-CVD.
摘要翻译：描述了通过HDP（高密度等离子体）CVD（化学气相沉积）沉积电介质层的改进方法。在电介质沉积期间，一种方法控制施加到侧源RF功率的RF功率小于约2500瓦。第二种方法控制HDP-CVD沉积介电层的厚度小于约2000和3000埃之间。介电层的HDP-CVD沉积的这些方法导致在通过HDP-CVD沉积介电层之后消除或抑制对MOSFET器件的等离子体诱导的损坏并改善MOSFET器件的栅极氧化物完整性。

29. 发明授权

US06620679B1 Method to integrate high performance 1T ram in a CMOS process using asymmetric structure 有权
标题翻译：使用不对称结构在CMOS工艺中集成高性能1T RAM的方法
公开(公告)号：US06620679B1
公开(公告)日：2003-09-16
申请号：US10224185
申请日：2002-08-20
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Dennis J. Sinitsky
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Dennis J. Sinitsky
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897
摘要： A high performance 1T RAM cell in a system-on-a-chip is formed using an asymmetric LDD structure that improves pass gate performance and storage node junction leakage. The asymmetric LDD structure is formed using selective ion implantation of the core and I/O LDDs. The node junctions are both pocket implant-free and source/drain implant-free. Further, silicide formation is avoided within the storage node junctions by forming nearly merged sidewall spacers within the node junctions and by forming optional blocking portions over the nearly merged sidewall spacers.
摘要翻译：使用非对称LDD结构形成片上系统中的高性能1T RAM单元，可提高通过栅极性能和存储节点结泄漏。使用核心和I / O LDD的选择性离子注入形成非对称LDD结构。节点结是无凹槽植入和无源植入。此外，通过在节点结内形成几乎合并的侧壁间隔物并且通过在几乎合并的侧壁间隔物上形成可选的阻挡部分，避免在储存节点结内形成硅化物。

30. 发明授权

US06376294B1 Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process 有权
标题翻译：在嵌入式DRAM工艺中，针脚区域的字线绑扎接触定义多边形骨的方法
公开(公告)号：US06376294B1
公开(公告)日：2002-04-23
申请号：US09755686
申请日：2001-01-08
申请人： Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Wen-Cheng Chen , Chen-Jong Wang
发明人： Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Wen-Cheng Chen , Chen-Jong Wang
IPC分类号： H01L218238
CPC分类号： H01L27/10891 , H01L21/823842 , H01L27/10894
摘要： A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region. At least one second mask layer portion is formed over the undoped poly segment within the LOGIC region and at least one third mask layer portion is formed over the doped poly segment in the portion of the stitch region within the DRAM region. The doped poly segment and undoped poly segment are etched to form: undoped poly periphery logic gate portions within the LOGIC region; doped poly dog-bone within the portion of the stitch region within the DRAM region; and doped poly word lines within the DRAM region. The second and third mask layer portions are stripped to expose the undoped poly periphery logic gate portions and the doped poly dog-bone.
摘要翻译：一种用于在DRAM器件中制造狗骨的方法，包括以下步骤。提供了具有形成有STI的上硅层的半导体结构。半导体结构具有LOGIC区域和其间具有缝合区域的DRAM区域。在半导体结构上形成多晶硅层。掺杂剂选择性地注入到DRAM区域内的多晶硅区域中，并且DRAM区域内的线圈区域的部分，以形成掺杂的多段，以及逻辑区域内的未掺杂的多段，以及缝合区域的部分在LOGIC区域内。在掺杂的多段和未掺杂的多段上形成硬掩模，并且被图案化以仅在DRAM区域内的字线掺杂的多段上形成至少一个图案化的第一硬掩模部分。至少一个第二掩模层部分形成在LOGIC区域内的未掺杂的多段上，并且至少一个第三掩模层部分形成在DRAM区域内的线迹区域的部分中的掺杂多晶片段上。蚀刻掺杂的多段和未掺杂的多段以在逻辑区内形成未掺杂的多边形逻辑门部; 在DRAM区域内的线圈区域的部分内的掺杂多晶骨; 和在DRAM区域内的掺杂多晶字线。剥离第二和第三掩模层部分以暴露未掺杂的多边形逻辑门部分和掺杂的多晶骨。

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