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21. 发明授权

US07394150B2 Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys 有权
标题翻译：半导体封装包括插入在杯形引线框架和具有台面和谷底的引线框架之间的管芯
公开(公告)号：US07394150B2
公开(公告)日：2008-07-01
申请号：US10996148
申请日：2004-11-23
申请人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Robert Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
发明人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Robert Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
IPC分类号： H01L23/52 , H01L29/40 , H01L21/302
CPC分类号： H01L23/49548 , H01L23/3107 , H01L23/49513 , H01L23/49562 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/84 , H01L2224/16245 , H01L2224/32245 , H01L2224/37147 , H01L2224/40245 , H01L2224/73253 , H01L2224/83801 , H01L2224/84385 , H01L2224/84801 , H01L2924/01004 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
摘要翻译：半导体封装包括在上引线框架和下引线框架之间插入倒装芯片的管芯。下引线框架具有与芯片底表面上的端子对准的触点。上引线框架接触管芯顶部的端子，并且上引线框架的边缘围绕模具的边缘向下弯曲，使上引线框架成杯形。上引线框架的边缘接触下引线框架的另一部分，使得封装的所有触点是共面的，并且可以表面安装在印刷电路板上。芯片的端子通过焊料层电连接到引线框架。预定了将管芯与引线框架连接的各个焊料层的厚度，以通过许多热循环来优化封装的性能。这是通过用多个台面制造下引线框架并使用双重回流焊工艺来完成的。

22. 发明授权

US07238551B2 Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys 有权
标题翻译：在具有台面和谷部的杯形引线框架之间制造包括管芯的半导体封装的方法
公开(公告)号：US07238551B2
公开(公告)日：2007-07-03
申请号：US10996149
申请日：2004-11-23
申请人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Robert Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
发明人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Robert Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
IPC分类号： H01L21/00
CPC分类号： H01L23/49562 , H01L23/49524 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/83 , H01L2224/16245 , H01L2224/26175 , H01L2224/291 , H01L2224/32245 , H01L2224/37147 , H01L2224/40245 , H01L2224/73153 , H01L2224/73253 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2224/83801 , H01L2224/84801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
摘要翻译：半导体封装包括在上引线框架和下引线框架之间插入倒装芯片的管芯。下引线框架具有与芯片底表面上的端子对准的触点。上引线框架接触管芯顶部的端子，并且上引线框架的边缘围绕模具的边缘向下弯曲，使上引线框架成杯形。上引线框架的边缘接触下引线框架的另一部分，使得封装的所有触点是共面的，并且可以表面安装在印刷电路板上。芯片的端子通过焊料层电连接到引线框架。预定了将管芯与引线框架连接的各个焊料层的厚度，以通过许多热循环来优化封装的性能。这是通过用多个台面制造下引线框架并使用双重回流焊工艺来完成的。

23. 发明申请

US20070063340A1 Complete power management system implemented in a single surface mount package 有权
标题翻译：完整的电源管理系统在单个表面贴装封装中实现
公开(公告)号：US20070063340A1
公开(公告)日：2007-03-22
申请号：US11479619
申请日：2006-06-30
申请人： King Owyang , Mohammed Kasem , Yuming Bai , Frank Kuo , Sen Mao , Sam Kuo
发明人： King Owyang , Mohammed Kasem , Yuming Bai , Frank Kuo , Sen Mao , Sam Kuo
IPC分类号： H01L23/34
CPC分类号： G05F3/08 , H01L23/36 , H01L23/49861 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0106 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H02M3/00 , H02M3/04 , H05K1/0206 , H05K1/0218 , H05K1/141 , H05K1/181 , H05K3/202 , H05K3/284 , H05K3/3436 , H05K7/20409 , H05K7/205 , H05K2201/10166 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.
摘要翻译：在单个表面贴装封装中实现的完整的电源管理系统。该系统可被绘制到DC-DC转换器系统，并且在无引线表面贴装封装中包括驱动器/控制器，MOSFET晶体管，无源元件（例如，电感器，电容器，电阻器）和可选的二极管。在各种实施例中，MOSFET晶体管可以由绝缘栅双极晶体管，IGBT替代。该系统还可以是电源管理系统，智能电源模块或运动控制系统。无源组件可以连接在引线框连接之间。可以使用金属夹接合技术将有源部件耦合到引线框架。在一个实施例中，暴露的金属底部可以用作有效散热器。

24. 发明申请

US20060110856A1 Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys 有权
标题翻译：在具有台面和谷部的杯形引线框架之间制造包括管芯的半导体封装的方法
公开(公告)号：US20060110856A1
公开(公告)日：2006-05-25
申请号：US10996149
申请日：2004-11-23
申请人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
发明人： Mohammed Kasem , King Owyang , Frank Kuo , Serge Jaunay , Sen Mao , Oscar Ou , Peter Wang , Chang-Sheng Chen
IPC分类号： H01L21/44
CPC分类号： H01L23/49562 , H01L23/49524 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/83 , H01L2224/16245 , H01L2224/26175 , H01L2224/291 , H01L2224/32245 , H01L2224/37147 , H01L2224/40245 , H01L2224/73153 , H01L2224/73253 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2224/83801 , H01L2224/84801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.
摘要翻译：半导体封装包括在上引线框架和下引线框架之间插入倒装芯片的管芯。下引线框架具有与芯片底表面上的端子对准的触点。上引线框架接触管芯顶部的端子，并且上引线框架的边缘围绕模具的边缘向下弯曲，使上引线框架成杯形。上引线框架的边缘接触下引线框架的另一部分，使得封装的所有触点是共面的，并且可以表面安装在印刷电路板上。芯片的端子通过焊料层电连接到引线框架。预定了将管芯与引线框架连接的各个焊料层的厚度，以通过许多热循环来优化封装的性能。这是通过用多个台面制造下引线框架并使用双重回流焊工艺来完成的。

25. 发明授权

US5404040A Structure and fabrication of power MOSFETs, including termination structures 失效
标题翻译：功率MOSFET的结构和制造，包括端接结构
公开(公告)号：US5404040A
公开(公告)日：1995-04-04
申请号：US96135
申请日：1993-07-22
申请人： Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan V. D. Linde
发明人： Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan V. D. Linde
IPC分类号： H01L21/28 , H01L21/316 , H01L21/322 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78 , H01L29/68 , H01L21/265
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/28167 , H01L21/31662 , H01L21/3221 , H01L29/1095 , H01L29/66712 , H01L29/7811 , H01L21/28211 , H01L29/0619 , H01L29/0696 , H01L29/402 , H01L29/4238
摘要： A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.
摘要翻译：功率MOSFET由具有主有源区和外围端接区的半导体主体（2000和2001）产生。基本上均匀厚度的第一绝缘层（2002）位于活性和终止区域之上。主要多晶部分（2003A / 2003B）位于主要在有效区域之上的第一绝缘层之上。第一和第二外围多晶段（2003C1和2003C2）位于终止区域上方的第一绝缘层上。栅电极（2016）与主多晶部分接触。源电极（2015A / 2015B）接触有源区，端接区和第一多晶段。可选的附加金属部分（2019）接触第二多晶段。 MOSFET通常由五掩模工艺制成。在金属沉积和图案化之后执行失真蚀刻以限定两个外围多晶段。

26. 发明授权

US5429964A Low on-resistance power MOS technology 失效
标题翻译：制造电源的方法
公开(公告)号：US5429964A
公开(公告)日：1995-07-04
申请号：US180265
申请日：1994-01-12
申请人： Hamza Yilmaz , Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan Van Der Linde
发明人： Hamza Yilmaz , Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan Van Der Linde
IPC分类号： H01L21/28 , H01L21/316 , H01L21/322 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78 , H01L21/335
CPC分类号： H01L21/28167 , H01L21/02129 , H01L21/02238 , H01L21/02255 , H01L21/28211 , H01L21/31662 , H01L21/3221 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/66712 , H01L29/7802 , H01L29/7811
摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.
摘要翻译：通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。以这种方式，三维扩散效果被最小化，避免了穿孔。讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集。栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

27. 发明授权

US5521409A Structure of power mosfets, including termination structures 失效
标题翻译：功率MOSFET结构，包括端接结构
公开(公告)号：US5521409A
公开(公告)日：1996-05-28
申请号：US362674
申请日：1994-12-22
申请人： Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan Van Der Linde
发明人： Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan Van Der Linde
IPC分类号： H01L21/28 , H01L21/316 , H01L21/322 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78 , H01L29/68
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/28167 , H01L21/31662 , H01L21/3221 , H01L29/1095 , H01L29/66712 , H01L29/7811 , H01L21/28211 , H01L29/0619 , H01L29/0696 , H01L29/402 , H01L29/4238
摘要： A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.
摘要翻译：功率MOSFET由具有主有源区和外围端接区的半导体主体（2000和2001）产生。典型地具有基本均匀厚度的第一绝缘层（2002）位于活性和终止区域之上。主要多晶部分（2003A / 2003B）位于主要在有效区域之上的第一绝缘层之上。第一和第二外围多晶段（2003C1和2003C2）位于终止区域上方的第一绝缘层上。栅电极（2016）与主多晶部分接触。源电极（2015A / 2015B）接触有源区，端接区和第一多晶段。可选的附加金属部分（2019）接触第二多晶段。在这种情况下，第二多晶段在终止区域的划线部分上延伸，以便在划线操作期间划线。

28. 发明授权

US5304831A Low on-resistance power MOS technology 失效
标题翻译：低导通电阻MOS技术
公开(公告)号：US5304831A
公开(公告)日：1994-04-19
申请号：US881589
申请日：1992-05-12
申请人： Hamza Yilmaz , Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan Van Der Linde
发明人： Hamza Yilmaz , Fwu-Iuan Hshieh , Mike Chang , Jun W. Chen , King Owyang , Dorman C. Pitzer , Jan Van Der Linde
IPC分类号： H01L21/28 , H01L21/316 , H01L21/322 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/78 , H01L27/01
CPC分类号： H01L21/28167 , H01L21/02129 , H01L21/02238 , H01L21/02255 , H01L21/28211 , H01L21/31662 , H01L21/3221 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/66712 , H01L29/7802 , H01L29/7811
摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.
摘要翻译：通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。以这种方式，三维扩散效果被最小化，避免了穿孔。讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集。栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

29. 发明授权

US08269263B2 High current density power field effect transistor 有权
标题翻译：高电流密度功率场效应晶体管
公开(公告)号：US08269263B2
公开(公告)日：2012-09-18
申请号：US12119367
申请日：2008-05-12
申请人： Jian Li , King Owyang
发明人： Jian Li , King Owyang
IPC分类号： H01L27/105
CPC分类号： H01L27/085 , H01L29/0623 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/47 , H01L29/7828 , H01L29/8083
摘要： An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.
摘要翻译：超短通道混合功率场效应晶体管（FET）器件允许电流从体硅流入，而无npn寄生。该器件没有机身，但仍具有在高额定电流下具有低正向电压的体二极管。该器件包括JFET部件，与JFET部件相邻设置的第一累积MOSFET，以及在沟槽端的底部邻近JFET部件设置的第二累积MOSFET，或具有连接源极的隔离栅极的MOSFET。

30. 发明授权

US07033876B2 Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same 有权
标题翻译：沟槽MIS器件具有植入的漏极漂移区域和厚的底部氧化物及其制造方法
公开(公告)号：US07033876B2
公开(公告)日：2006-04-25
申请号：US10326311
申请日：2002-12-19
申请人： Mohamed N. Darwish , King Owyang
发明人： Mohamed N. Darwish , King Owyang
IPC分类号： H01L21/8238 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/20
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L21/823487 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368
摘要： A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The relatively flat dopant profile in the channel region provides an increased punchthrough voltage and low threshold voltage.
摘要翻译：沟槽MIS器件形成在覆盖在N +衬底上的P外延层中。在一个实施例中，器件包括在沟槽底部的厚氧化物层和从沟槽的底部延伸到衬底的N型漏 - 漂移区。厚的绝缘层减小了栅极和漏极之间的电容，从而提高了器件在高频下工作的能力。优选地，漏极漂移区域至少部分地通过在沟槽的侧壁上制造间隔物并且在侧壁间隔物之间并通过沟槽的底部注入N型掺杂剂而形成。厚的底部氧化物层形成在沟槽的底部，同时侧壁间隔物仍然在位。因此，在漏极 - 漂移区的注入之后，工艺的热预算受到限制的实施例中，漏 - 漂移区和外延层之间的PN结与厚的底部氧化物的边缘自对准。漏极漂移区可以比在N外延层中形成的常规“漂移区”更重的掺杂。因此，器件具有低导通电阻。通道区域中相对平坦的掺杂物分布提供了增加的穿通电压和低阈值电压。

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