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21. 发明授权

US5964876A Program-invocation-count measuring system, program-invocation-count measuring method, and medium for storing program-invocation-count measuring software 失效
标题翻译：程序调用计数测量系统，程序调用计数测量方法和用于存储程序调用计数测量软件的介质
公开(公告)号：US5964876A
公开(公告)日：1999-10-12
申请号：US968073
申请日：1997-11-12
申请人： Eisuke Shimomura , Munehiro Yoshida
发明人： Eisuke Shimomura , Munehiro Yoshida
IPC分类号： G06F11/34 , G06F1/00 , G06F13/00 , G06F15/00 , G06F21/00 , G06F12/14
CPC分类号： G06F21/121
摘要： In a program-invocation-count measuring system, first and second identification codes are acquired and exchanged among processes as a broadcast or response signal. The first identification code is used for determining whether there are currently active processes which have been activated by invoking the same program. On the other hand, the second identification code is used for determining whether a response signal received by a process is the same as a broadcast signal transmitted earlier by the process.
摘要翻译：在程序调用计数测量系统中，作为广播或响应信号在进程之间获取和交换第一和第二识别码。第一识别码用于确定是否通过调用相同的程序激活了当前活动的进程。另一方面，第二识别码用于确定由处理接收到的响应信号是否与通过该处理较早发送的广播信号相同。

22. 发明授权

US5231607A Semiconductor memory device 失效
公开(公告)号：US5231607A
公开(公告)日：1993-07-27
申请号：US599973
申请日：1990-10-19
申请人： Munehiro Yoshida , Syuso Fujii
发明人： Munehiro Yoshida , Syuso Fujii
IPC分类号： H01L27/10 , G11C5/14 , G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： G11C5/14
摘要： A semiconductor memory device has a memory cell array region, a plurality of signal lines arranged above the memory cell array region, and a plurality of power-supply lines or grounding lines, each of which has a first end and a second end and which are arranged between the signal lines in a similar pattern to that of the signal lines.

23. 发明授权

US07789558B2 Thermal sensing circuit using bandgap voltage reference generators without trimming circuitry 有权
标题翻译：使用带有微调电路的带隙电压基准发生器的热感测电路
公开(公告)号：US07789558B2
公开(公告)日：2010-09-07
申请号：US12402357
申请日：2009-03-11
申请人： Munehiro Yoshida , David William Boerstler
发明人： Munehiro Yoshida , David William Boerstler
IPC分类号： G01K7/01 , G01K3/02
CPC分类号： G05F3/30
摘要： Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.
摘要翻译：提供了使用不使用修整电路的带隙电压参考发生器的方法，系统和热感测装置。此外，提供了根据本发明的电路，系统和方法，其不使用大量的芯片空间并且不需要单独的热敏元件。

24. 发明申请

US20090174468A1 Thermal Sensing Circuit Using Bandgap Voltage Reference Generators Without Trimming Circuitry 有权
标题翻译：使用带隙参考发生器的热传感电路，无需修整电路
公开(公告)号：US20090174468A1
公开(公告)日：2009-07-09
申请号：US12402357
申请日：2009-03-11
申请人： Munehiro Yoshida , David William Boerstler
发明人： Munehiro Yoshida , David William Boerstler
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.
摘要翻译：提供了使用不使用修整电路的带隙电压参考发生器的方法，系统和热感测装置。此外，提供了根据本发明的电路，系统和方法，其不使用大量的芯片空间并且不需要单独的热敏元件。

25. 发明授权

US07427158B2 Advanced thermal sensor 有权
标题翻译：先进的热传感器
公开(公告)号：US07427158B2
公开(公告)日：2008-09-23
申请号：US11034644
申请日：2005-01-13
申请人： Munehiro Yoshida
发明人： Munehiro Yoshida
IPC分类号： G01K7/01 , G01K7/14
CPC分类号： G01K3/005 , G01K7/01
摘要： Systems and methods for reducing the complexity and size of thermal sensors, where the voltage of a thermally sensitive device is compared to a reference voltage that varies as a function of temperature, rather than being constant. One embodiment comprises a thermal sensing system including a reference voltage generator, a thermal sensor and a comparator. The reference voltage generator is configured to generate a non-constant reference voltage that varies as a known function of temperature. The thermal sensor is configured to generate a sensor voltage that also varies as a known function of temperature. The functions of the reference and sensor voltages cross at a known temperature/voltage. The comparator is configured to compare the sensor voltage and the reference voltage and to generate a comparison output signal based on the comparison of the sensor voltage and the first reference voltage. A transition in this signal indicates the reference temperature.
摘要翻译：用于降低热传感器的复杂性和尺寸的系统和方法，其中将热敏元件的电压与作为温度的函数变化的参考电压进行比较，而不是恒定。一个实施例包括包括参考电压发生器，热传感器和比较器的热感测系统。参考电压发生器被配置为产生作为已知温度函数而变化的非恒定参考电压。热传感器被配置为产生也随温度已知功能而变化的传感器电压。参考电压和传感器电压的功能在已知的温度/电压下交叉。比较器被配置为比较传感器电压和参考电压，并且基于传感器电压和第一参考电压的比较来产生比较输出信号。此信号中的转换表示参考温度。

26. 发明授权

US07187053B2 Thermal sensing method and system 失效
标题翻译：热感测方法及系统
公开(公告)号：US07187053B2
公开(公告)日：2007-03-06
申请号：US10606586
申请日：2003-06-26
申请人： David William Boerstler , Munehiro Yoshida
发明人： David William Boerstler , Munehiro Yoshida
IPC分类号： H01L31/058
CPC分类号： H01L27/0248 , G01K1/026 , G01K3/14 , G01K7/01
摘要： The present invention provides an integrated circuit. The integrated circuit has a plurality of chip areas. The integrated circuit also has a plurality of temperature sensors, at least one per chip area. The temperature sensors generate a voltage proportional to the measured temperature. A voltage comparator compares the voltage output of the plurality of temperature sensors. The voltage comparator is further employable to generate a signal if the difference between the voltages generated by the plurality of temperature sensors exceeds a threshold.
摘要翻译：本发明提供一种集成电路。集成电路具有多个芯片区域。集成电路还具有多个温度传感器，至少每个芯片面积一个。温度传感器产生与测量温度成比例的电压。电压比较器比较多个温度传感器的电压输出。如果由多个温度传感器产生的电压差超过阈值，电压比较器还可用于产生信号。

27. 发明授权

US06570801B2 Semiconductor memory having refresh function 失效
公开(公告)号：US06570801B2
公开(公告)日：2003-05-27
申请号：US09981517
申请日：2001-10-16
申请人： Munehiro Yoshida , Hiroshi Shinya
发明人： Munehiro Yoshida , Hiroshi Shinya
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.

28. 发明授权

US06301144B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06301144B1
公开(公告)日：2001-10-09
申请号：US09650745
申请日：2000-08-30
申请人： Munehiro Yoshida , Yohji Watanabe
发明人： Munehiro Yoshida , Yohji Watanabe
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/10 , G11C7/1051
摘要： A memory chip is comprises memory cells and, for example, 16 amplifiers, each having a first output terminal and a second output terminal. The 16 amplifiers are connected at the first output terminal to 16 first-type signal lines RD(0) to RD(15) and at the second output terminal to four second-type signal lines bTRD(0) to bTRD(3) in increment fashion. More precisely, the second output terminals of every four amplifiers are connected the four second-type signal lines, respectively. A coincidence/non-coincidence determining circuit determines how the potentials of the second-type signal lines bTRD(0) to bTRD(3) and the potentials of the first-type signal lines RD(0) to RD(15) connected to all amplifiers that are connected to the second-type signal lines change when all data items of the same polarity are read from memory cells. Hence, a compressed-data test can be performed thereby compressing 16-bit data into 4-bit data by using only 20 signal lines.
摘要翻译：存储器芯片包括存储器单元和例如16个放大器，每个具有第一输出端子和第二输出端子。 16个放大器在第一输出端子连接到16个第一类型信号线RD（0）至RD（15），在第二输出端连接到四个第二类型信号线bTRD（0）至bTRD（3）时尚。更准确地说，每四个放大器的第二输出端分别连接四个第二类信号线。一致/不一致确定电路确定第二类型信号线bTRD（0）至bTRD（3）的电位和第一类信号线RD（0）至RD（15）的电位如何连接到所有当从存储器单元读取相同极性的所有数据项时，连接到第二类型信号线的放大器改变。因此，可以执行压缩数据测试，从而通过仅使用20个信号线将16位数据压缩成4位数据。

29. 发明授权

US5561630A Data sense circuit for dynamic random access memories 失效
标题翻译：用于动态随机存取存储器的数据检测电路
公开(公告)号：US5561630A
公开(公告)日：1996-10-01
申请号：US535704
申请日：1995-09-28
申请人： Daisuke Katoh , Toshiaki Kirihata , Munehiro Yoshida
发明人： Daisuke Katoh , Toshiaki Kirihata , Munehiro Yoshida
IPC分类号： G11C11/409 , G11C7/10 , G11C11/4091 , G11C11/4094 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4094 , G11C11/4091 , G11C7/1006 , G11C2207/002 , G11C2207/005
摘要： An improved data sense for a DRAM. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.
摘要翻译：改进了DRAM的数据检测。每个位线对通过一对高电阻通过门耦合到感测放大器。在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对中的一个。因此，数据从感测放大器传递到第二读出放大器和芯片外。数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。

30. 发明授权

US5367487A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5367487A
公开(公告)日：1994-11-22
申请号：US101701
申请日：1993-08-04
申请人： Munehiro Yoshida
发明人： Munehiro Yoshida
IPC分类号： G11C11/413 , G11C5/14 , G11C11/403 , G11C11/407 , G11C11/409 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C11/40
CPC分类号： G11C5/147
摘要： An external source voltage is received by a semiconductor memory chip. A first source voltage corresponding to the external source voltage and a second source voltage which is lower than the first source voltage are supplied to an internal circuit of the semiconductor memory chip. The memory chip includes a memory cell array section, having at least a sense amplifier, and a peripheral circuit. The first source voltage is supplied to the memory cell array section when data is transferred between the semiconductor memory chip and an external device, and the second source voltage is supplied thereto to read and write data within the semiconductor memory chip when data is maintained only. The first source voltage is supplied to the peripheral circuit, when the second source voltage is supplied to the memory cell array section to maintain data.
摘要翻译：外部源极电压由半导体存储器芯片接收。对应于外部源极电压的第一源极电压和低于第一源极电压的第二源极电压被提供给半导体存储器芯片的内部电路。存储器芯片包括至少具有读出放大器和外围电路的存储单元阵列部分。当在半导体存储器芯片和外部设备之间传送数据时，第一源电压被提供给存储单元阵列部分，并且当仅保持数据时，第二源极电压被提供给半导体存储器芯片内的数据。当第二源电压被提供给存储单元阵列部分以保持数据时，第一源电压被提供给外围电路。

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