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21. 发明授权

US07923367B2 Multilayer wiring substrate mounted with electronic component and method for manufacturing the same 有权
标题翻译：安装有电子部件的多层布线基板及其制造方法
公开(公告)号：US07923367B2
公开(公告)日：2011-04-12
申请号：US11907889
申请日：2007-10-18
申请人： Yoshihiro Machida
发明人： Yoshihiro Machida
IPC分类号： H01L21/4763
CPC分类号： H05K1/186 , H01L23/13 , H01L23/49822 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H05K3/4602 , H05K2201/09845 , H05K2203/049 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A multilayer wiring substrate mounted with an electronic component includes an electronic component, a core material layer having a first opening for accommodating the electronic component, a resin layer which is formed on one surface of the core material layer and which has a second opening greater than the first opening, a supporting layer which is formed on the other surface of the core material layer and which supports the electronic component, a plurality of connection conductor sections which are provided around the first opening and within the second opening on the one surface of the core material layer, bonding wires for electrically connecting the electronic component to the connection conductor sections, and a sealing resin filled into the first and second openings in order to seal the electronic component and the bonding wires.
摘要翻译：安装有电子部件的多层布线基板包括电子部件，具有容纳电子部件的第一开口的芯材层，形成在芯材层的一个面上的树脂层，其具有大于所述第一开口，形成在所述芯材料层的另一个表面上并且支撑所述电子部件的支撑层，多个连接导体部，所述多个连接导体部设置在所述第一开口的周围，并且位于所述第一开口的一个表面上芯材料层，用于将电子部件电连接到连接导体部分的接合线以及填充到第一和第二开口中的密封树脂，以密封电子部件和接合线。

22. 发明授权

US07786580B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07786580B2
公开(公告)日：2010-08-31
申请号：US11870743
申请日：2007-10-11
申请人： Yoshihiro Machida , Takaharu Yamano
发明人： Yoshihiro Machida , Takaharu Yamano
IPC分类号： H01L21/60
CPC分类号： H01L23/3114 , H01L21/6835 , H01L23/485 , H01L23/525 , H01L24/11 , H01L24/12 , H01L2221/68359 , H01L2221/68363 , H01L2221/68377 , H01L2224/0231 , H01L2224/02319 , H01L2224/02333 , H01L2224/0401 , H01L2224/13099 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014
摘要： A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.
摘要翻译：半导体芯片的特征在于包括其上形成有电极焊盘的半导体芯片的结构，形成在各个电极焊盘上的凸起，并且具有突出部分，形成在半导体芯片上的绝缘层和要连接的导电图案到凸块，其中突出部分的末端插入到导电图案中，并且插入的末端被平坦化。

23. 发明授权

US07772109B2 Manufacturing method of multilayer wiring substrate 有权
标题翻译：多层布线基板的制造方法
公开(公告)号：US07772109B2
公开(公告)日：2010-08-10
申请号：US11724265
申请日：2007-03-15
申请人： Yoshihiro Machida
发明人： Yoshihiro Machida
IPC分类号： H01L21/4763
CPC分类号： H05K3/4614 , H05K1/0393 , H05K3/0052 , H05K3/28 , H05K3/4602 , H05K3/4635 , H05K2201/0195 , H05K2201/055 , H05K2201/09536 , H05K2203/061
摘要： A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second structural body 22 to a second structural body 62 and the first multilayer wiring structural body 16 is electrically connected to the second multilayer wiring structural body 56.
摘要翻译：在基板101的两个表面101A，101B上同时形成第一多层布线结构体16和第二多层布线结构体56，然后将对应于第三区域C1的结构体120的部分折叠成与第二结构体22与第二结构体62和第一多层布线结构体16电连接到第二多层布线结构体56。

24. 发明授权

US07772091B2 Manufacturing method of semiconductor apparatus comprising alignment patterns in scribe regions 有权
标题翻译：包括划线区域中的取向图案的半导体装置的制造方法
公开(公告)号：US07772091B2
公开(公告)日：2010-08-10
申请号：US12212169
申请日：2008-09-17
申请人： Yoshihiro Machida
发明人： Yoshihiro Machida
IPC分类号： H01L21/304
CPC分类号： H01L23/544 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L2223/5442 , H01L2223/5446 , H01L2224/0231 , H01L2224/02333 , H01L2224/0401 , H01L2224/05624 , H01L2224/13099 , H01L2224/274 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： Alignment patterns are formed in scribe regions of a semiconductor substrate, and through grooves for exposing the scribe regions are disposed in an insulating layer formed on the semiconductor substrate. Formation positions of wiring patterns are aligned based on the alignment patterns, and a metal layer is patterned and the wiring patterns are formed.
摘要翻译：在半导体衬底的划线区域中形成对准图案，并且通过用于暴露刻划区域的沟槽设置在形成在半导体衬底上的绝缘层中。基于对准图案对配线图案的形成位置进行图案化，形成配线图案。

25. 发明申请

US20090309231A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090309231A1
公开(公告)日：2009-12-17
申请号：US12485601
申请日：2009-06-16
申请人： Yoshihiro Machida
发明人： Yoshihiro Machida
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L21/563 , H01L21/4857 , H01L23/3128 , H01L23/49822 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes: a first insulating layer having an opening therethrough; a first wiring pattern disposed on the first insulating layer; an external connection terminal provided on a portion of the first wiring pattern exposed from the opening; a second insulating layer which covers the first wiring pattern and having via holes therethrough; a second wiring pattern disposed within the second insulating layer and electrically connected to the first wiring pattern via a conductive material filled in at least one of the via holes; a semiconductor element having an electrode thereon and mounted on the second insulating layer to be electrically connected to the first wiring pattern through the electrode disposed in at least one of the via holes; an underfill resin filled between the semiconductor element and the second insulating layer; and a sealing resin portion which seals the semiconductor element.
摘要翻译：半导体器件包括：具有穿过其中的开口的第一绝缘层; 布置在所述第一绝缘层上的第一布线图案; 设置在从所述开口露出的所述第一布线图案的一部分上的外部连接端子; 第二绝缘层，其覆盖所述第一布线图案并且具有穿过其的通孔; 第二布线图案，设置在所述第二绝缘层内并且经由填充在至少一个所述通孔中的导电材料电连接到所述第一布线图案; 半导体元件，其上具有电极，并且安装在第二绝缘层上，以通过布置在至少一个通孔中的电极电连接到第一布线图案; 填充在所述半导体元件和所述第二绝缘层之间的底部填充树脂; 以及密封半导体元件的密封树脂部分。

26. 发明申请

US20090127665A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090127665A1
公开(公告)日：2009-05-21
申请号：US12273901
申请日：2008-11-19
申请人： Takaharu Yamano , Yoshihiro Machida
发明人： Takaharu Yamano , Yoshihiro Machida
IPC分类号： H01L21/304 , H01L23/58
CPC分类号： H01L21/78 , H01L23/3114 , H01L23/3192 , H01L23/49816 , H01L24/10 , H01L2224/02333 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05647 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/00014
摘要： A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.
摘要翻译：一种制造半导体器件的方法，具有制备具有多个半导体芯片形成区域的半导体衬底和布置在多个半导体芯片形成区域之间并包括衬底切割位置的划线区域的准备步骤，半导体芯片形成步骤在所述多个半导体芯片形成区域上形成具有电极焊盘的半导体芯片，在所述半导体芯片上形成第一绝缘层和所述半导体基板的划线区域的第一绝缘层形成步骤，形成第二绝缘层形成工序，除了与基板切断位置对应的区域之外的第一绝缘层上的绝缘层，以及在基板切断位置切断半导体基板的切断工序。

27. 发明授权

US07521283B2 Manufacturing method of chip integrated substrate 有权
标题翻译：芯片集成基板的制造方法
公开(公告)号：US07521283B2
公开(公告)日：2009-04-21
申请号：US11257717
申请日：2005-10-25
申请人： Yoshihiro Machida , Takaharu Yamano
发明人： Yoshihiro Machida , Takaharu Yamano
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/2402 , H01L2224/24226 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/00
摘要： A manufacturing method of a chip integrated substrate is disclosed. The manufacturing method includes a first step that forms a wiring structure to be connected to a semiconductor chip on a first core substrate; a second step that disposes the semiconductor chip on a second core substrate; and a third step that bonds the first core substrate on which the wiring structure is formed to the second core substrate on which the semiconductor chip is disposed. In addition, the manufacturing method includes a step that removes the first core substrate after the third step and a step that removes the second core substrate after the third step.
摘要翻译：公开了一种芯片集成基板的制造方法。该制造方法包括：形成与第一芯基板上的半导体芯片连接的布线结构的第一工序; 将所述半导体芯片配置在第二芯基板上的第二工序; 以及将其上形成有布线结构的第一芯基板结合到其上设置有半导体芯片的第二芯基板的第三步骤。此外，该制造方法包括在第三步骤之后去除第一芯基板的步骤和在第三步骤之后去除第二芯基板的步骤。

28. 发明授权

US08062571B2 Resin sealing method in stacked wiring substrate 有权
标题翻译：堆叠布线基板中的树脂密封方法
公开(公告)号：US08062571B2
公开(公告)日：2011-11-22
申请号：US12573293
申请日：2009-10-05
申请人： Yoshihiro Machida
发明人： Yoshihiro Machida
IPC分类号： B29C45/02 , B29C45/14
CPC分类号： B29C45/14655 , B29C33/56 , B29C45/14836 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05644 , H01L2224/05655 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A resin sealing device includes a lower die, an upper die which is arranged over the lower die, on a lower surface side of which a concave portion is provided, and to a bottom surface peripheral portion of the concave portion of which a projection portion projecting toward an opening portion side of the concave portion to raise partially a bottom surface is provided, and a protection film provided on a lower surface side of the upper die and adhered along a concave surface of the concave portion by adsorbing, wherein the stacked wiring substrate is sealed with a resin by making a fused resin flow into a cavity including a space between the stacked wiring substrate from a resin supplying portion, in a state that the stacked wiring substrate in which a plurality of wiring substrates are stacked via connection bumps is arranged and sandwiched between the lower die and the concave portion of the upper die.
摘要翻译：树脂密封装置包括：下模，设置在下模上的上模，其下表面侧设置有凹部，并且在凹部的底表面周边部分突出部分突出设置在凹部的开口部侧，部分地形成底面，并且设置在上模的下表面侧并通过吸附沿着凹部的凹面粘合的保护膜，其中，叠层布线基板在通过连接凸块堆叠多个布线基板的堆叠布线基板的状态下，使树脂熔融树脂流入包括从树脂供给部分的堆叠的布线基板之间的空间的空腔中，并且夹在下模和上模的凹部之间。

29. 发明申请

US20110000331A1 BALL-TYPE SPEED REDUCER AND ROTARY TABLE DEVICE USING THE SAME 有权
标题翻译：球型减速器和旋转台装置
公开(公告)号：US20110000331A1
公开(公告)日：2011-01-06
申请号：US12920646
申请日：2009-02-17
申请人： Yoshio Iwase , Masahiro Machida , Yoshihiro Machida
发明人： Yoshio Iwase , Masahiro Machida , Yoshihiro Machida
IPC分类号： F16H1/16
CPC分类号： F16H1/163 , B23Q2220/004 , F16H55/10 , F16H55/24
摘要： Provided are a ball-type speed reducer and a rotary table device that are capable of performing high-speed rotation and high-rigidity rotation and suitable for reduction in size and weight. An index table 10 includes a ball-type speed reducer 20 and a table 50 that is fixed to an upper surface of a worm wheel 30 of the ball-type speed reducer 20. When the worm gear 22 rotates as the input shaft 24 of the ball-type speed reducer 20 rotates, balls 36 made of a magnetic material move along a ball groove 26 having a spiral shape. The worm wheel 30 rotates as the balls 36 move, and the table 50 rotates. The balls 36 are attracted and held by the permanent magnet 34 on the worm wheel 30 side, so that a case for preventing the balls 36 from coming off the worm wheel 30 can be omitted, whereby the total size and weight can be reduced. Backlash is not required, so that high-speed rotation and high-rigidity rotation are possible.
摘要翻译：提供能够进行高速旋转和高刚性旋转的球型减速器和旋转台装置，适合于减小尺寸和重量。分度表10包括球形减速器20和固定到球型减速器20的蜗轮30的上表面的工作台50.当蜗轮22作为输入轴24旋转时，球型减速器20旋转，由磁性材料制成的球36沿着具有螺旋形状的球槽26移动。蜗轮30随着滚珠36移动而旋转，并且台子50旋转。滚珠36被蜗轮30侧的永久磁铁34吸引并保持，从而可以省略防止滚珠36从蜗轮30脱落的壳体，能够减小总尺寸和重量。不需要间隙，因此可以进行高速旋转和高刚性旋转。

30. 发明授权

US07624501B2 Method of manufacturing multilayer wiring board 有权
标题翻译：多层布线板的制造方法
公开(公告)号：US07624501B2
公开(公告)日：2009-12-01
申请号：US12068270
申请日：2008-02-05
申请人： Yoshihiro Machida
发明人： Yoshihiro Machida
IPC分类号： H05K3/10
CPC分类号： H05K3/462 , H05K3/4647 , H05K2201/10234 , H05K2203/063 , H05K2203/0733 , H05K2203/1327 , H05K2203/167 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156
摘要： First, a plurality of wiring boards are fabricated at separate steps. The first wiring board includes a Cu post formed on a wiring layer on one surface of a substrate, and a first stopper layer formed at a desired position around the Cu post. The second wiring board includes a through hole for insertion of the Cu post therethrough, a connection terminal formed on a wiring layer on one surface of a substrate, and a second stopper layer that engages the first stopper layer and functions to suppress in-plane misalignment. The third wiring board includes a connection terminal formed on a wiring layer on one surface of a substrate. Then, the wiring boards are stacked up, as aligned with one another so that the wiring layers are interconnected via the Cu post and the connection terminals, to thereby electrically connect the wiring boards. Thereafter, resin is filled into gaps between the wiring boards.
摘要翻译：首先，以分开的步骤制造多个布线板。第一布线板包括形成在基板的一个表面上的布线层上的Cu柱和形成在Cu柱周围的期望位置的第一阻挡层。第二布线板包括用于插入Cu柱的通孔，形成在基板的一个表面上的布线层上的连接端子和与第一阻挡层接合并用于抑制面内未对准的功能的第二阻挡层。第三布线板包括形成在基板的一个表面上的布线层上的连接端子。然后，将布线基板彼此对准地堆叠起来，使得布线层经由铜柱和连接端子互连，从而电连接布线板。此后，将树脂填充到布线板之间的间隙中。

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