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21. 发明授权

US08450713B2 Nonvolatile semiconductor memory device and manufacturing method for same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08450713B2
公开(公告)日：2013-05-28
申请号：US12713223
申请日：2010-02-26
申请人： Nobuyoshi Awaya , Yoshiji Ohta , Yoshiaki Tabuchi
发明人： Nobuyoshi Awaya , Yoshiji Ohta , Yoshiaki Tabuchi
IPC分类号： H01L45/00 , H01L21/822
CPC分类号： H01L27/249 , G11C13/0007 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/0688 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L45/1616
摘要： A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.
摘要翻译：具有两个具有可变电阻元件的端子的存储单元的三维存储单元阵列被形成为：在Z方向上相邻的存储单元的一端连接到沿Z方向延伸的中间选择线之一，在X和Y方向上对齐 ; 位于Z方向相同点的存储单元的另一端连接到在Z方向上排列的第三选择线之一; 选择晶体管在X和Y方向上排列的二维阵列与Z方向上的存储单元阵列相邻; 在X方向上相邻的选择晶体管的栅极，在Y方向相邻的选择晶体管的漏极和选择晶体管的源极分别连接到相同的第一选择线，第二选择线和不同的中间选择线; 并且第一，第二和第三选择线分别连接到X，Y和Z解码器。

22. 发明授权

US08422270B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08422270B2
公开(公告)日：2013-04-16
申请号：US13044892
申请日：2011-03-10
申请人： Suguru Kawabata , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
发明人： Suguru Kawabata , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C2013/0045 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
摘要翻译：非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路，每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

23. 发明申请

US20120069626A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120069626A1
公开(公告)日：2012-03-22
申请号：US13215594
申请日：2011-08-23
申请人： Takashi Nakano , Yukio Tamai , Nobuyoshi Awaya
发明人： Takashi Nakano , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： G11C11/00
CPC分类号： G11C29/028 , G11C13/0007 , G11C13/0033 , G11C13/0035 , G11C2013/0083 , G11C2029/0409 , G11C2029/0411
摘要： The invention provides a semiconductor memory device including a variable resistance element capable of decreasing a variation of a resistance value of stored data due to a large number of times of switching operations and capable of performing a stable writing operation. The device has a circuit that applies a reforming voltage pulse to a memory cell including a variable resistance element of a degraded switching characteristic and a small read margin due to a large number of times of application of a write voltage pulse, to return each resistance state of the variable resistance element to an initial resistance state. By applying the reforming voltage pulse, the variable resistance element can recover at least one resistance state from a variation from the initial resistance state, and can recover the switching characteristic. Accordingly, there is obtained a semiconductor memory device in which a reduction of a read margin is suppressed.
摘要翻译：本发明提供了一种包括可变电阻元件的半导体存储器件，该可变电阻元件能够由于大量的开关操作而减少存储数据的电阻值的变化并且能够执行稳定的写入操作。该装置具有电路，该电路将重整电压脉冲施加到由于施加写入电压脉冲的次数多的包括具有劣化的开关特性的可变电阻元件和小的读取余量的存储单元，以使每个电阻状态的可变电阻元件到初始电阻状态。通过施加重整电压脉冲，可变电阻元件可以从初始电阻状态的变化恢复至少一个电阻状态，并且可以恢复开关特性。因此，获得了抑制读取余量的减小的半导体存储器件。

24. 发明申请

US20090273964A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090273964A1
公开(公告)日：2009-11-05
申请号：US12515286
申请日：2007-11-05
申请人： Shinobu Yamazaki , Yasunari Hosoi , Nobuyoshi Awaya , Shinichi Sato , Kenichi Tanaka
发明人： Shinobu Yamazaki , Yasunari Hosoi , Nobuyoshi Awaya , Shinichi Sato , Kenichi Tanaka
IPC分类号： G11C11/00 , G11C7/00 , H01L29/47
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A nonvolatile semiconductor memory device comprises: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends, a transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than a first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage; a load circuit connected to the variable resistive element in series having an adjustable load resistance; and a voltage generation circuit for applying a voltage to both ends of a serial circuit; wherein the variable resistive element can transit between the states by adjusting a resistance of the load circuit.
摘要翻译：非易失性半导体存储器件包括：二端结构可变电阻元件，其中由两端的电流 - 电压特性限定的电阻特性通过向两端施加满足预定条件的电压来稳定地在低电阻状态和高电阻状态之间转变，通过施加绝对值等于或高于第一阈值电压的第一极性的电压而发生到高电阻状态的低电阻状态，并且通过施加绝对值为或等于或等于或等于或等于或等于或等于高于第二阈值电压; 连接到具有可调负载电阻的串联可变电阻元件的负载电路; 以及用于向串联电路的两端施加电压的电压产生电路; 其中可变电阻元件可以通过调节负载电路的电阻在状态之间转变。

25. 发明授权

US07433222B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07433222B2
公开(公告)日：2008-10-07
申请号：US11647329
申请日：2006-12-29
申请人： Yasunari Hosoi , Nobuyoshi Awaya , Isao Inoue
发明人： Yasunari Hosoi , Nobuyoshi Awaya , Isao Inoue
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/003 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/72 , G11C2213/76 , G11C2213/79
摘要： A nonvolatile semiconductor device is configured so that a load circuit applying voltage to a variable resistive element is provided electrically connecting in series to the variable resistive element, a load resistive characteristic of the load circuit can be switched between two different characteristics. The two load resistive characteristics are selectively switched depending on whether a resistive characteristic of the variable resistive element transits from low resistance state to high resistance state, or vice versa, voltage necessary for transition from one of the two resistive characteristics to the other is applied by applying writing voltage to a serial circuit of the variable resistive element and load circuit. After the resistive characteristic of the variable resistive element transits from one to the other, voltage applied to the variable resistive element does not allow a resistive characteristic to return from the other to one depending on the selected load resistive characteristic.
摘要翻译：非易失性半导体器件被配置为使得向可变电阻元件施加电压的负载电路被提供为电连接到可变电阻元件，负载电路的负载电阻特性可以在两个不同特性之间切换。根据可变电阻元件的电阻特性是否从低电阻状态转变为高电阻状态，反之亦然，两个负载电阻特性被选择性地切换，或者反过来，通过两个电阻特性之一转换到另一个电阻特性所需的电压被施加对可变电阻元件和负载电路的串联电路施加写入电压。在可变电阻元件的电阻特性从一个转变到另一个之后，施加到可变电阻元件的电压根据所选择的负载电阻特性不允许电阻特性从另一个返回到一个。

26. 发明授权

US07236388B2 Driving method of variable resistance element and memory device 有权
标题翻译：可变电阻元件和存储器件的驱动方法
公开(公告)号：US07236388B2
公开(公告)日：2007-06-26
申请号：US11169535
申请日：2005-06-28
申请人： Yasunari Hosoi , Yukio Tamai , Kazuya Ishihara , Shinji Kobayashi , Nobuyoshi Awaya
发明人： Yasunari Hosoi , Yukio Tamai , Kazuya Ishihara , Shinji Kobayashi , Nobuyoshi Awaya
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C13/0007 , G11C13/0069 , G11C29/50008 , G11C2013/009 , G11C2213/31
摘要： A variable resistance element is configured to be provided with a perovskite-type oxide between a first electrode and a second electrode, of which electric resistance between the first electrode and the second electrode is changed by applying a voltage pulse of a predetermined polarity between the first electrode and the second electrode, and the variable resistance element has a resistance hysteresis characteristic, in which a changing rate of a resistance value is changed from positive to negative with respect to increase of a cumulative pulse applying time in the application of the voltage pulse. The voltage pulse is applied to the variable resistance element so that the cumulative pulse applying time is not longer than a specific cumulative pulse applying time, in which the changing rate of the, resistance value is changed from positive to negative with respect to increase of the cumulative pulse applying time in the resistance hysteresis characteristic.
摘要翻译：可变电阻元件被配置为在第一电极和第二电极之间设置有钙钛矿型氧化物，其中通过在第一电极和第二电极之间施加预定极性的电压脉冲来改变第一电极和第二电极之间的电阻电极和第二电极，并且可变电阻元件具有电阻滞后特性，其中电阻值的变化率相对于施加电压脉冲的累积脉冲施加时间的增加而从正变化到负。电压脉冲被施加到可变电阻元件，使得累积脉冲施加时间不长于特定的累积脉冲施加时间，其中电阻值的变化率相对于增加的电阻值从正变化到负累积脉冲施加时间在电阻滞后特性。

27. 发明申请

US20050040482A1 EPIR device and semiconductor devices utilizing the same 失效
标题翻译： EPIR器件和利用其的半导体器件
公开(公告)号：US20050040482A1
公开(公告)日：2005-02-24
申请号：US10790238
申请日：2004-03-02
申请人： Toshimasa Suzuki , Yuji Nishi , Masayuki Fujimoto , Nobuyoshi Awaya , Kohji Inoue , Keizo Sakiyama
发明人： Toshimasa Suzuki , Yuji Nishi , Masayuki Fujimoto , Nobuyoshi Awaya , Kohji Inoue , Keizo Sakiyama
IPC分类号： H01F10/32 , G11C13/00 , H01F41/18 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L43/10 , H01L43/12 , H01L45/00 , H01L27/108
CPC分类号： G11C13/0007 , B82Y10/00 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： There is provided an EPIR device which is excellent in mass productivity and high in practical utility. The EPIR device includes a lower electrode layer, a CMR thin film layer and an upper electrode layer which are laminated in this order on any of various substrates. A Pt polycrystal thin film 10 forming the lower electrode layer includes columnar Pt crystal grains 10A, 10B, 10C, . . . and over 90% of these crystal grains is oriented to a (1 1 1) face. Columnar PCMO crystal grain groups 20A, 20B, 20C, . . . are respectively locally grown epitaxially on the respective outermost surfaces of the Pt crystal grains 10A, 10B, 10C, Then, the crystal faces of the crystal grains included in the PCMO crystal grain groups 20A, 20B, 20C, . . . and vertical in the substrate surface normal direction are any one of (1 0 0)p, (1 1 0)p and (1 1 1)p planes.
摘要翻译：提供了具有优异的批量生产率和高实用性的EPIR装置。 EPIR器件包括下列电极层，CMR薄膜层和上电极层，它们以任何各种衬底依次层叠。形成下电极层的Pt多晶薄膜10包括柱状Pt晶粒10A，10B，10C。。。并且超过90％的这些晶粒取向为（111）面。柱状PCMO晶粒组20A，20B，20C。。。分别在Pt晶粒10A，10B，10C的各个最外表面上外延地局部生长。然后，包含在PCMO晶粒组20A，20B，20C中的晶粒的晶面。。。并且在衬底表面法线方向垂直是（110）p，（110）p和（111）p平面中的任何一个。

28. 发明授权

US5316796A Process for growing a thin metallic film 失效
标题翻译：生长薄金属薄膜的工艺
公开(公告)号：US5316796A
公开(公告)日：1994-05-31
申请号：US665610
申请日：1991-03-07
申请人： Nobuyoshi Awaya , Yoshinobu Arita
发明人： Nobuyoshi Awaya , Yoshinobu Arita
IPC分类号： C23C16/18 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/04 , C23C16/06
CPC分类号： C23C16/4557 , C23C16/18 , C23C16/4482 , C23C16/45565
摘要： A chemical vapor deposition process for growing a thin metallic film of copper or gold on a substrate includes providing a starting material composed of a .beta.-ketonato type metal complex of gold or copper in a heated container; preparing a carrier gas for the starting material which is composed of hydrogen as a reducing agent and at least one electron donating substance which bonds to and forms a molecular compound with the starting material by donating an electron to the starting material; passing a flow of the carrier gas through the heated container containing the starting material to form the molecular compound in situ and provide a flow of a gas mixture; introducing the flow of the gas mixture into a reaction chamber in which a substrate is positioned; and growing gold or copper on the substrate by thermally decomposing the molecular compound and any remaining starting material under temperature conditions effective therefor.
摘要翻译：用于在衬底上生长铜或金的薄金属膜的化学气相沉积方法包括在加热的容器中提供由β-酮型金属或铜的金属络合物组成的起始材料; 制备由氢气作为还原剂的起始材料的载气和通过向起始原料中提供电子而与原料结合并与原料形成分子化合物的至少一种给电子物质; 使载气的流动通过含有原料的加热容器，以便原位形成分子化合物并提供气体混合物流; 将气体混合物的流动引入到其中定位基板的反应室中; 并通过在有效的温度条件下热分解分子化合物和任何剩余的起始材料，在基底上生长金或铜。

29. 发明授权

US4660068A Substrate structure of semiconductor device and method of manufacturing the same 失效
标题翻译：半导体器件的基板结构及其制造方法
公开(公告)号：US4660068A
公开(公告)日：1987-04-21
申请号：US525570
申请日：1983-08-22
申请人： Kazuhito Sakuma , Yoshinobu Arita , Masaaki Sato , Nobuyoshi Awaya
发明人： Kazuhito Sakuma , Yoshinobu Arita , Masaaki Sato , Nobuyoshi Awaya
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/762 , H01L29/73 , H01L27/12
CPC分类号： H01L21/76 , H01L21/76229 , H01L21/76232
摘要： A substrate structure utilized to fabricate a semiconductor device is constituted by a silicon substrate; an element region selectively formed on the silicon substrate and a relatively thick field oxide region formed adjacent to the element region; an element isolating region formed between the element region and the field oxide region, the element isolating region being in direct contact with the field oxide region; the element isolating region being provided with a relatively deep groove formed in the silicon substrate and having a relatively small width; a silicon oxide insulating film formed on the inner wall of the groove; and a silicon nitride insulating film disposed on the silicon oxide insulating film. The surfaces of the element region, the element isolating region and the field oxide region on the silicon substrate are formed substantially flat.
摘要翻译：用于制造半导体器件的衬底结构由硅衬底构成; 选择性地形成在所述硅衬底上的元件区域和与所述元件区域相邻形成的相对厚的场氧化物区域; 形成在所述元件区域和所述场氧化物区域之间的元件隔离区域，所述元件隔离区域与所述场氧化物区域直接接触; 所述元件隔离区域设置有形成在所述硅衬底中并且具有相对较小宽度的相对较深的沟槽; 形成在所述槽的内壁上的氧化硅绝缘膜; 以及设置在氧化硅绝缘膜上的氮化硅绝缘膜。元件区域，元件隔离区域和硅衬底上的场氧化物区域的表面基本上平坦地形成。

30. 发明授权

US08411488B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08411488B2
公开(公告)日：2013-04-02
申请号：US13233301
申请日：2011-09-15
申请人： Suguru Kawabata , Shinobu Yamazaki , Kazuya Ishihara , Junya Onishi , Nobuyoshi Awaya , Yukio Tamai
发明人： Suguru Kawabata , Shinobu Yamazaki , Kazuya Ishihara , Junya Onishi , Nobuyoshi Awaya , Yukio Tamai
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/79
摘要： A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，用于存储通过布置存储单元而提供的用户数据，每个存储单元具有可变电阻元件，该可变电阻元件具有第一电极，第二电极和夹在第一和第二电极之间的金属氧化物制成的可变电阻器。第一和第二电极由与可变电阻器形成欧姆结的导电材料和分别与可变电阻器形成非欧姆结的导电材料形成。可变电阻器通过在电极之间施加电压而在两个或多个不同的电阻状态之间变化。改变后的电阻状态保持非挥发性。在存储单元阵列用于存储用户数据之前，将存储单元阵列中的所有存储单元的可变电阻元件设置为处于未使用状态的两个或多个不同电阻状态中的最高值。

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