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21. 发明授权

US5423285A Process for fabricating materials for ferroelectric, high dielectric constant, and integrated circuit applications 失效
标题翻译：用于制造铁电，高介电常数和集成电路应用材料的工艺
公开(公告)号：US5423285A
公开(公告)日：1995-06-13
申请号：US981133
申请日：1992-11-24
申请人： Carlos A. Paz de Araujo , Joseph D. Cuchiaro , Michael C. Scott , Larry D. McMillan
发明人： Carlos A. Paz de Araujo , Joseph D. Cuchiaro , Michael C. Scott , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C01G35/00 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L41/24 , H05K3/10 , C30B25/02
CPC分类号： H01L27/10805 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C26/02 , C30B29/68 , C30B7/00 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/11502 , H01L28/56 , H01L28/60 , H01L41/316 , H01L41/318 , H01L28/55 , H05K3/105
摘要： A precursor comprising a metal 2-ethylhexanoate in a xylenes solvent is applied to an integrated circuit wafer. The wafer is baked to dry the precursor, annealed to form a layered superlattice material on the wafer, then the integrated circuit is completed. If the metal is titanium, the precursor comprises titanium 2-methoxyethoxide having at least a portion of its 2-methoxyethoxide ligands replaced by 2-ethylhexanoate. If the metal is a highly electropositive element, the solvent comprises 2-methoxyethanol. If the metal is lead, bismuth, thallium, or antimony, 1% to 75% excess metal is included in the precursor to account for evaporation of the oxide during baking and annealing.
摘要翻译：将包含二甲苯溶剂中的2-乙基己酸金属的前体施加到集成电路晶片。将晶片烘烤以干燥前体，退火以在晶片上形成层状超晶格材料，然后完成集成电路。如果金属是钛，前体包括其2-甲氧基乙醇化物配体的至少一部分被2-乙基己酸酯取代的2-甲氧基乙氧基钛。如果金属是高电中性元素，则溶剂包括2-甲氧基乙醇。如果金属是铅，铋，铊或锑，则前体中含有1％至75％的过量金属，以便在焙烧和退火过程中氧化物的蒸发。

22. 发明授权

US5439845A Process for fabricating layered superlattice materials and making electronic devices including same 失效
公开(公告)号：US5439845A
公开(公告)日：1995-08-08
申请号：US350323
申请日：1994-12-05
申请人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
发明人： Hitoshi Watanabe , Carlos A. Paz De Araujo , Hiroyuki Yoshimori , Michael C. Scott , Takashi Mihara , Joseph D. Cuchiaro , Larry D. McMillan
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C26/02 , C30B7/00 , H01C7/10 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/108 , H01L27/115 , H01L41/24 , H05K3/10 , H01L29/15
CPC分类号： B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B29/68 , C30B7/00 , C30B7/005 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L27/11507 , H01L28/56 , H01L28/60 , H01L41/317 , H01L28/55 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

23. 发明授权

US06559469B1 Ferroelectric and high dielectric constant transistors 失效
标题翻译：铁电和高介电常数晶体管
公开(公告)号：US06559469B1
公开(公告)日：2003-05-06
申请号：US09686552
申请日：2000-10-11
申请人： Carlos A. Paz de Araujo , Larry D. McMillan , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro
发明人： Carlos A. Paz de Araujo , Larry D. McMillan , Vikram Joshi , Narayan Solayappan , Joseph D. Cuchiaro
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , C23C16/448 , C23C16/45561 , C23C18/1216 , C23C18/14 , C30B7/00 , C30B7/005 , C30B29/68 , G11C11/22 , G11C11/223 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/60
摘要： An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
摘要翻译：集成电路包括具有公式A1w1 + a1A2w2 + a2的分层超晶格材料。。。 Ajwj + ajS1x1 + s1S2x2 + s2。。。 Skxk + skB1y1 + b1B2y2 + b2。。。 Blyl + blQz-q，其中A1，A2。。。 Aj代表钙钛矿结构中的A位元素，S1，S2。。。 Sk代表超晶格发生器元件B1，B2。。。 B1表示钙钛矿结构中的B位元素，Q表示阴离子，上标表示各元素的化合价，下标表示单元中元素的原子数，并且至少w1和y1为非零。这些材料中的一些是非常低的疲劳铁电体，并且被应用在非易失性存储器中的铁电FET中。其他的是高介电常数材料，其在长期使用中不会劣化或分解，并且作为在绝缘体中的栅绝缘体。

24. 发明授权

US06225656B1 Ferroelectric integrated circuit with protective layer incorporating oxygen and method for fabricating same 有权
标题翻译：含有保护层的铁电集成电路和氧气的制造方法
公开(公告)号：US06225656B1
公开(公告)日：2001-05-01
申请号：US09204033
申请日：1998-12-01
申请人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
发明人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L2924/0002 , H01L2924/00
摘要： A protective layer in a ferroelectric integrated circuit contains small amounts of oxygen to protect ferroelectric oxide material against hydrogen degradation during the fabrication process. Typically, the protective layer is a hydrogen diffusion barrier layer formed to cover a thin film of ferroelectric oxide material. In one method, a small amount of oxygen is included in the sputter atmosphere during deposition of a hydrogen diffusion barrier or a metallized wiring layer. The oxygen forms oxides that inhibit diffusion of hydrogen towards the ferroelectric oxide material. The oxygen forms a concentration gradient so that the oxygen concentration in the interior of the protective layer is zero, and the oxygen concentration near the surfaces of the layer is about two weight percent.
摘要翻译：铁电集成电路中的保护层含有少量的氧以保护铁电氧化物材料在制造过程中抵抗氢降解。通常，保护层是形成为覆盖铁电氧化物材料的薄膜的氢扩散阻挡层。在一种方法中，在沉积氢扩散阻挡层或金属化布线层期间，溅射气氛中包含少量的氧。氧形成抑制氢向铁电氧化物材料扩散的氧化物。氧形成浓度梯度，使得保护层内部的氧浓度为零，并且层表面附近的氧浓度为约2重量％。

25. 发明授权

US06570202B2 Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same 有权
标题翻译：对氢曝露具有低灵敏度的铁电集成电路及其制造方法
公开(公告)号：US06570202B2
公开(公告)日：2003-05-27
申请号：US09779391
申请日：2001-02-07
申请人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
发明人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/75
摘要： A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.
摘要翻译：在集成电路中的铁电薄膜的上方形成氢阻挡层。氢阻挡层直接在铁电薄膜的受保护部分之上，而铁电薄膜的牺牲段横向延伸超过氢阻挡层的边缘。牺牲段吸收氢，使得其不能横向扩散到铁电薄膜的受保护段中。在吸收氢之后，牺牲段被蚀刻掉以允许电连接到其下方的电路层。铁电薄膜优选包含层状超晶格化合物。添加到铌酸铋钽酸锶化合物的标准前体溶液中的过量铋或铌有助于降低铁电性能的氢降解。

26. 发明授权

US06512256B1 Integrated circuit having self-aligned hydrogen barrier layer and method for fabricating same 有权
标题翻译：具有自对准氢阻挡层的集成电路及其制造方法
公开(公告)号：US06512256B1
公开(公告)日：2003-01-28
申请号：US09197385
申请日：1998-11-20
申请人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
发明人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
IPC分类号： H01L31119
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： In an integrated circuit, a stack of thin film layers comprising respectively a bottom electrode, a thin film of metal oxide, a top electrode, a lower barrier-adhesion layer, a hydrogen barrier layer, and an upper barrier-adhesion layer are patterned to form a memory capacitor capped with a self-aligned hydrogen barrier layer. Preferably, the top and bottom electrodes comprise platinum, the metal oxide material comprises ferroelectric layered superlattice material, the upper and lower barrier-adhesion layers comprise titanium, and the hydrogen barrier layer comprises titanium nitride. The hydrogen barrier layer inhibits diffusion of hydrogen, thereby preventing hydrogen degradation of the metal oxides. Part of the upper barrier-adhesion layer is removed in order to increase the electrical conductivity in the layer. Preferably, the memory capacitor is a ferroelectric nonvolatile memory. Preferably, the layered superlattice material includes strontium bismuth tantalate or strontium bismuth tantalum niobate.
摘要翻译：在集成电路中，将包括底部电极，金属氧化物薄膜，顶部电极，下部阻挡层 - 粘合层，氢气阻挡层和上部阻挡 - 粘附层的薄膜层叠层图案化形成用自对准氢阻挡层封盖的记忆电容器。优选地，顶部和底部电极包括铂，金属氧化物材料包括铁电层状超晶格材料，上部和下部阻挡 - 粘附层包含钛，氢气阻挡层包括氮化钛。氢阻挡层抑制氢的扩散，从而防止金属氧化物的氢降解。为了增加层中的导电性，去除了上部阻挡 - 粘附层的一部分。优选地，存储电容器是铁电非易失性存储器。优选地，层状超晶格材料包括钽酸铋钽或铌酸铋钽铌酸盐。

27. 发明授权

US06365927B1 Ferroelectric integrated circuit having hydrogen barrier layer 有权
标题翻译：具有氢阻挡层的铁电集成电路
公开(公告)号：US06365927B1
公开(公告)日：2002-04-02
申请号：US09541290
申请日：2000-04-03
申请人： Joseph D. Cuchiaro , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Joseph D. Cuchiaro , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L28/55 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of metal oxide material in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following nitrides: aluminum titanium nitride (Al2Ti3N6), aluminum silicon nitride (Al2Si3N6), aluminum niobium nitride (AlNb3N6), aluminum tantalum nitride (AlTa3N6), aluminum copper nitride (Al2Cu3N4), tungsten nitride (WN), and copper nitride (Cu3N2). The thin film of metal oxide is ferroelectric or high-dielectric, nonferroelectric material. Preferably, the metal oxide comprises ferroelectric layered superlattice material. Preferably, the hydrogen barrier layer is located directly over the thin film of metal oxide.
摘要翻译：集成电路中的氢扩散阻挡层位于集成电路中以抑制氢扩散到金属氧化物材料的薄膜。氢扩散阻挡层包括以下氮化物中的至少一种：氮化钛铝（Al 2 Ti 3 N 6），氮化硅铝（Al 2 Si 3 N 6），氮化铌（AlNb 3 N 6），氮化钽铝（AlTa 3 N 6），氮化铝铝（Al 2 Cu 3 N 4）（WN）和氮化铜（Cu3N2）。金属氧化物的薄膜是铁电或高电介质非电介质材料。优选地，金属氧化物包括铁电层状超晶格材料。优选地，氢阻挡层位于金属氧化物的薄膜的正上方。

28. 发明授权

US06339238B1 Ferroelectric field effect transistor, memory utilizing same, and method of operating same 失效
标题翻译：铁电场效应晶体管，利用其的存储器及其操作方法
公开(公告)号：US06339238B1
公开(公告)日：2002-01-15
申请号：US09329670
申请日：1999-06-10
申请人： Myoungho Lim , Vikram Joshi , Joseph D. Cuchiaro , Larry D. McMillan , Carlos A. Paz de Araujo
发明人： Myoungho Lim , Vikram Joshi , Joseph D. Cuchiaro , Larry D. McMillan , Carlos A. Paz de Araujo
IPC分类号： H01L2972
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/223 , H01L21/28291 , H01L27/0629 , H01L29/78391
摘要： A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. A cell is selected for writing or reading by application of bias voltages to the source, drain, gate or substrate. A gate voltage equal to one truth table logic value and a drain voltage equal to another truth table logic value are applied via a row decoder, and a substrate bias equal to a third truth table logic value is applied via a column decoder to write to the memory a resultant Ids logic state, which can be non-destructively read by placing a voltage across the source and drain.
摘要翻译：一种铁电非易失性存储器，其中每个存储单元由单个电子元件，铁电FET组成。 FET包括源极，漏极，栅极和衬底。通过对源极，漏极，栅极或衬底施加偏置电压来选择单元进行写入或读取。通过行解码器施加等于一个真值表逻辑值的栅极电压和等于另一个真值表逻辑值的漏极电压，经由列解码器施加等于第三真值表逻辑值的衬底偏置以写入记录结果Ids逻辑状态，通过在源极和漏极之间放置电压可以非破坏性地读取。

29. 发明授权

US06207465B1 Method of fabricating ferroelectric integrated circuit using dry and wet etching 失效
标题翻译：使用干法和湿蚀刻制作铁电集成电路的方法
公开(公告)号：US06207465B1
公开(公告)日：2001-03-27
申请号：US09062248
申请日：1998-04-17
申请人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
发明人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/28568 , H01L21/32132 , H01L21/32134 , H01L21/32136 , H01L27/1085 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： In a ferroelectric integrated circuit, a hydrogen barrier layer comprising titanium or titanium nitride or both is formed over a metal oxide element to protect it from hydrogen degradation. After hydrogen annealing and other process steps causing hydrogenating or reducing conditions, the hydrogen barrier layer is removed in a two-step etching process. The first etch step is a dry etch, preferably a standard ion-mill etching process, which rapidly removes most of the hydrogen barrier layer. The second step is a wet, chemical etch, preferably using a solution containing NH4OH, H2O2, and H2O, which selectively removes remnants of the hydrogen barrier layer from the circuit by oxidizing a chemical element of the barrier layer. The metal oxide material preferably comprises a layered superlattice compound.
摘要翻译：在铁电集成电路中，在金属氧化物元件上形成包含钛或氮化钛或二者的氢阻挡层，以防止其降解氢。在氢退火和引起氢化或还原条件的其它工艺步骤之后，在两步蚀刻工艺中除去氢气阻挡层。第一蚀刻步骤是干蚀刻，优选标准离子磨蚀刻蚀工艺，其快速去除大部分氢阻挡层。第二步是湿化学蚀刻，优选使用含有NH 4 OH，H 2 O 2和H 2 O的溶液，其通过氧化阻挡层的化学元素从电路中选择性地除去氢阻挡层的残余物。金属氧化物材料优选包含层状超晶格化合物。

30. 发明授权

US6130103A Method for fabricating ferroelectric integrated circuits 失效
标题翻译：铁电集成电路的制造方法
公开(公告)号：US6130103A
公开(公告)日：2000-10-10
申请号：US62283
申请日：1998-04-17
申请人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
发明人： Joseph D. Cuchiaro , Akira Furuya , Carlos A. Paz de Araujo , Yoichi Miyasaka
IPC分类号： G11C11/22 , H01L21/28 , H01L21/314 , H01L21/316 , H01L27/115 , H01L21/00 , H01L21/8242
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/28291 , H01L21/31691 , H01L27/11507 , H01L28/55 , H01L21/324 , H01L28/56
摘要： An integrated circuit is formed that contains a ferroelectric element comprising metal oxide material containing at least two metals. Various methods and structures are applied to minimize the degradation of ferroelectric properties caused by hydrogen during fabrication of the circuit. Oxygen is added to the some elements of the integrated circuit to serve as a getter of hydrogen during fabrication steps. To minimize hydrogen degradation, the ferroelectric compound can be fabricated from a liquid precursor containing one or more of the constituent metals in excess of the amount corresponding to a stoichiometrically balanced concentration. A hydrogen barrier layer, preferably comprising titanium nitride, is formed to cover the top of the ferroelectric element. A hydrogen heat treatment in hydrogen gas is performed on the integrated circuit at a temperature from 200.degree. to 350.degree. C. and for a time period not exceeding 30 minutes to minimize degradation of the ferroelectric properties by hydrogen while restoring other properties of the integrated circuit. An oxygen recovery anneal at 800.degree. C. after high-energy hydrogen steps restores ferroelectric properties.
摘要翻译：形成集成电路，其包含含有至少两种金属的金属氧化物材料的铁电体元件。应用各种方法和结构以最小化在电路制造期间由氢引起的铁电性能的劣化。在制造步骤期间，将氧气添加到集成电路的一些元件以用作氢气的吸气剂。为了使氢降解最小化，铁电化合物可以由含有一种或多种构成金属的液体前体制成，超过对应于化学计量平衡浓度的量。形成优选包含氮化钛的氢阻挡层以覆盖铁电元件的顶部。在集成电路中在200〜350℃的温度下进行氢气中的氢热处理，并且在不超过30分钟的时间内对氢的铁电性质的降低最小化，同时恢复集成电路的其它性能。在高能氢步骤之后，在800℃下的氧回收退火恢复铁电性能。

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