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21. 发明授权

US5969420A Semiconductor device comprising a plurality of interconnection patterns 失效
标题翻译：包括多个互连图案的半导体器件
公开(公告)号：US5969420A
公开(公告)日：1999-10-19
申请号：US881397
申请日：1997-06-24
申请人： Shigehiro Kuge , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Shigehiro Kuge , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L23/528 , H01L25/04 , H01L25/18 , H01L27/02 , H01L27/04 , H01L27/108 , H01L23/48
CPC分类号： H01L23/5286 , H01L27/0207 , H01L27/10897 , H01L2924/0002 , H01L2924/3011
摘要： On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.
摘要翻译：在构成NAND门的晶体管P1，P2，N1和N2上，堆叠具有高熔点金属的互连图案W和铝互连图案Al1和Al2。用于将晶体管P1，P2，N1和N2相互连接的本地线路LL通过具有高熔点金属的互连图形W，在与非门与外部之间的信号输入/输出的信号线SL和SL'形成由铝互连图案Al1形成，并且用于将电源电位Vcc和Vss施加到NAND门的电源线VL和VL'由铝互连图案Al2形成。与通过铝互连图案Al1形成局部线LL的现有技术相比，可以提高布局的自由度，并且可以减小布局面积。

22. 发明授权

US06404056B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06404056B1
公开(公告)日：2002-06-11
申请号：US09313249
申请日：1999-05-18
申请人： Shigehiro Kuge , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
发明人： Shigehiro Kuge , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
IPC分类号： H01L2940
CPC分类号： H01L23/5286 , H01L27/0207 , H01L27/10897 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL′ for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL′ for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.
摘要翻译：在构成NAND门的晶体管P1，P2，N1，N2上，堆叠具有高熔点金属的互连图案W和铝互连图案Al1和Al2。用于将晶体管P1，P2，N1和N2相互连接的本地线路LL通过具有高熔点金属的互连图案W，在与非门与外部之间的信号输入/输出的信号线SL和SL'形成由铝互连图案Al1形成，并且用于将电源电位Vcc和Vss施加到NAND门的电源线VL和VL'由铝互连图案Al2形成。与通过铝互连图案Al1形成局部线LL的现有技术相比，可以提高布局的自由度，并且可以减小布局面积。

23. 再颁专利

USRE36027E Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages 失效
标题翻译：具有位线对和独立设置为不同预充电电压的I / O线对的CSL系统的随机存取存储器
公开(公告)号：USRE36027E
公开(公告)日：1999-01-05
申请号：US664081
申请日：1996-06-13
申请人： Kazutami Arimoto , Kazuyasu Fujishima , Hideto Hidaka , Masaki Tsukude , Tsukasa Ohishi
发明人： Kazutami Arimoto , Kazuyasu Fujishima , Hideto Hidaka , Masaki Tsukude , Tsukasa Ohishi
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C11/4096 , G11C11/41 , H01L27/10 , G11C7/00
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/4096 , G11C7/1048
摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
摘要翻译：在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对。在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 + E，fra 1/2 + EE xVCC的电平与位线对相同。这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

24. 发明授权

US5321657A Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages 失效
标题翻译：具有位线对和独立设置为不同预充电电压的I / O线对的CSL系统的随机存取存储器
公开(公告)号：US5321657A
公开(公告)日：1994-06-14
申请号：US865145
申请日：1992-04-08
申请人： Kazutami Arimoto , Kazuyasu Fujishima , Hideto Hidaka , Masaki Tsukude , Tsukasa Ohishi
发明人： Kazutami Arimoto , Kazuyasu Fujishima , Hideto Hidaka , Masaki Tsukude , Tsukasa Ohishi
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C11/4096 , G11C11/41 , H01L27/10 , G11C7/00
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/4096 , G11C7/1048
摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
摘要翻译：在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对。在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 1 / 2xVCC的电平与位线对相同。这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

25. 发明授权

US5249155A Semiconductor device incorporating internal voltage down converting circuit 失效
标题翻译：包含内部电压降低转换电路的半导体器件
公开(公告)号：US5249155A
公开(公告)日：1993-09-28
申请号：US819208
申请日：1992-01-10
申请人： Kazutami Arimoto , Hideto Hidaka , Mikio Asakura , Masanori Hayashikoshi , Masaki Tsukude , Shinji Kawai , Tsukasa Ooishi
发明人： Kazutami Arimoto , Hideto Hidaka , Mikio Asakura , Masanori Hayashikoshi , Masaki Tsukude , Shinji Kawai , Tsukasa Ooishi
IPC分类号： H01L21/8234 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/409 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/11 , H03K17/30
CPC分类号： H03K17/302 , G05F1/465 , G11C5/147 , H01L2924/0002
摘要： An n channel driver circuit comprised of an N channel MOS transistor is provided in parallel to a driver circuit comprised of a P channel MOS transistor. Normally, n channel driver circuit supplies an internal supply voltage, to activate driver circuit only at the time of current peak. Thus, an insufficient capability of n.sup.- channel driver circuit to supply current is supplemented.
摘要翻译：由N沟道MOS晶体管构成的n沟道驱动电路与由P沟道MOS晶体管构成的驱动电路并联设置。通常，n通道驱动电路提供内部电源电压，仅在当前峰值时激活驱动电路。因此，补充了n沟道驱动电路不足以提供电流的能力。

26. 发明授权

US6069379A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6069379A
公开(公告)日：2000-05-30
申请号：US968897
申请日：1997-11-06
申请人： Hiroshi Kimura , Tadashi Nishimura , Takahiro Tsuruda , Kazutami Arimoto , Tadato Yamagata , Kazuyasu Fujishima
发明人： Hiroshi Kimura , Tadashi Nishimura , Takahiro Tsuruda , Kazutami Arimoto , Tadato Yamagata , Kazuyasu Fujishima
IPC分类号： H01L21/335 , H01L21/8239 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852
摘要： In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.
摘要翻译：在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。

27. 发明授权

US06214664B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06214664B1
公开(公告)日：2001-04-10
申请号：US09443016
申请日：1999-11-18
申请人： Hiroshi Kimura , Tadashi Nishimura , Takahiro Tsuruda , Kazutami Arimoto , Tadato Yamagata , Kazuyasu Fujishima
发明人： Hiroshi Kimura , Tadashi Nishimura , Takahiro Tsuruda , Kazutami Arimoto , Tadato Yamagata , Kazuyasu Fujishima
IPC分类号： H01L218242
CPC分类号： H01L27/10852
摘要： In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.
摘要翻译：在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。

28. 发明授权

US5909046A Semiconductor integrated circuit device having stable input protection circuit 失效
标题翻译：半导体集成电路器件具有稳定的输入保护电路
公开(公告)号：US5909046A
公开(公告)日：1999-06-01
申请号：US965618
申请日：1997-11-06
申请人： Tetsushi Tanizaki , Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
发明人： Tetsushi Tanizaki , Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L23/62
CPC分类号： H01L27/0248 , H01L24/05 , H01L2924/14
摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.
摘要翻译：导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏可以获得耐热性，并且可以获得耐喘振性的改善。

29. 发明授权

US06341098B2 Semiconductor integrated circuit device having hierarchical power source arrangement 有权
标题翻译：具有分层电源布置的半导体集成电路器件
公开(公告)号：US06341098B2
公开(公告)日：2002-01-22
申请号：US09846223
申请日：2001-05-02
申请人： Tadato Yamagata , Kazutami Arimoto , Masaki Tsukude
发明人： Tadato Yamagata , Kazutami Arimoto , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C7/22 , G11C8/08 , G11C11/4074 , H03K19/0016
摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.
摘要翻译：分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在列电路有效时间段。可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

30. 发明授权

US6150728A Semiconductor memory device having a pad arrangement with reduced occupying area 失效
标题翻译：半导体存储器件具有占用面积减小的衬垫装置
公开(公告)号：US6150728A
公开(公告)日：2000-11-21
申请号：US854754
申请日：1997-05-12
申请人： Masaki Tsukude , Kazutami Arimoto
发明人： Masaki Tsukude , Kazutami Arimoto
IPC分类号： G11C11/401 , H01L21/321 , H01L21/60 , H01L21/8242 , H01L23/495 , H01L23/50 , H01L27/105 , H01L27/108 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/50 , H01L27/105 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48245 , H01L2224/48247 , H01L2224/4826 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01024 , H01L2924/01033 , H01L2924/01046 , H01L2924/01082
摘要： On a surface of a semiconductor chip having a longer side and a shorter side, a line of a plurality of first pads and a line of a plurality of second pads are arranged in the shape of a cross. Upon multibit expansion, increase in length of the longer side of semiconductor chip can be suppressed even though the number of pads is increased by additionally providing the second pad. In addition, there is no need to reduce the pitch between pads. Thus, a semiconductor memory device allowing multibit expansion is provided without an increase in size of the chip and the pad or reduction in pitches between pads and between pins.
摘要翻译：在具有长边和短边的半导体芯片的表面上，多个第一焊盘的线和多个第二焊盘的线以交叉的形式布置。在多位扩展时，即使通过另外设置第二焊盘来增加焊盘的数量，也可以抑制半导体芯片的长边的长度的增加。此外，不需要减小垫之间的间距。因此，提供了允许多位扩展的半导体存储器件，而不增加芯片和焊盘的尺寸，或者减小焊盘之间和引脚之间的间距。

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