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21. 发明授权

US6103559A Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication 有权
标题翻译：为源/漏和LDD注入和随后的栅极制造做一次性通道掩蔽的方法
公开(公告)号：US6103559A
公开(公告)日：2000-08-15
申请号：US282033
申请日：1999-03-30
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L29/51 , H01L21/338 , H01L21/3205
CPC分类号： H01L21/28194 , H01L21/28052 , H01L21/28123 , H01L21/8221 , H01L21/823814 , H01L21/823828 , H01L27/0688 , H01L29/517 , H01L29/6659 , H01L21/28202 , H01L29/518 , H01L29/66545
摘要： A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.
摘要翻译：提供了一种用于制造半导体器件的方法，所述方法包括在结构之上形成第一介电层，并在第一介电层上形成牺牲层的岛。该方法还包括将第一掺杂剂引入到结构的第一部分中，留下由岛保护的结构的第二部分，以及去除离开岛的第二部分的岛的第一部分。该方法还包括将第二掺杂剂引入到结构的第一部分和第三部分中，留下结构的第四部分被岛的第二部分保护。该方法还包括形成与岛的第二部分相邻的第二电介质层，去除岛的第二部分，在结构的第四部分之上形成栅极电介质，并在栅极电介质上方形成栅极导体。

22. 发明授权

US6064102A Semiconductor device having gate electrodes with different gate insulators and fabrication thereof 失效
标题翻译：具有栅电极和不同栅极绝缘体的半导体器件及其制造
公开(公告)号：US6064102A
公开(公告)日：2000-05-16
申请号：US992318
申请日：1997-12-17
申请人： Mark I. Gardner , H. Jim Fulford , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , H. Jim Fulford , Thomas E. Spikes, Jr.
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L21/823462
摘要： A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.
摘要翻译：提供了具有不同栅极绝缘体的栅电极和制造这种器件的工艺的半导体器件。根据本发明的一个实施例，提供一种半导体器件，其中在衬底的第一区域上形成第一栅极绝缘体。与第一栅极绝缘体不同的第二栅极绝缘体形成在衬底的第二区域上。最后，在第一和第二栅极绝缘体的每一个上形成一个或多个栅电极。第一栅极绝缘体可以例如具有不同于第二栅极绝缘体的介电常数和/或厚度。例如，第一栅极绝缘体可以具有大于20的介电常数，并且第二栅极绝缘体可以具有小于10的介电常数。

23. 发明授权

US6060345A Method of making NMOS and PMOS devices with reduced masking steps 失效
标题翻译：制造具有减少掩蔽步骤的NMOS和PMOS器件的方法
公开(公告)号：US6060345A
公开(公告)日：2000-05-09
申请号：US844924
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
摘要翻译：公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层，栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中。有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

24. 发明授权

US6057583A Transistor with low resistance metal source and drain vertically displaced from the channel 有权
标题翻译：具有低电阻金属源和漏极的晶体管垂直从通道移位
公开(公告)号：US6057583A
公开(公告)日：2000-05-02
申请号：US227511
申请日：1999-01-06
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/266 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L29/417 , H01L29/49 , H01L29/76
CPC分类号： H01L29/66575 , H01L21/266 , H01L21/76895 , H01L21/823814 , H01L29/41775 , H01L29/41783 , H01L29/4966 , H01L29/66537 , H01L29/66545 , Y10S257/902
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operating speed.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。晶体管的栅极也可以由诸如金属的低电阻材料形成。晶体管的源极和漏极区域配置在半导体衬底上，并且晶体管沟道在衬底内。保护介电层沉积在半导体衬底上。源极/漏极沟槽形成在保护电介质层中，随后填充有牺牲电介质。位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。随后去除牺牲电介质并用优选由低电阻金属形成的源极/漏极区域代替。所得到的晶体管可以表现出低接触和串联电阻，并且提高了操作速度。

25. 发明授权

US6051487A Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode 失效
标题翻译：使用用于限定栅电极的区域的牺牲插塞的半导体器件制造
公开(公告)号：US6051487A
公开(公告)日：2000-04-18
申请号：US993612
申请日：1997-12-18
申请人： Mark I. Gardner , H. Jim Fulford , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , H. Jim Fulford , Mark C. Gilmer , Robert Paiz
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L21/3205
CPC分类号： H01L21/28194 , H01L21/28238 , H01L29/495 , H01L29/517 , H01L29/66545 , H01L29/66575 , H01L29/6659 , H01L29/66537
摘要： A semiconductor device is formed by forming a sacrificial plug over a substrate and forming active regions in the substrate adjacent the sacrificial plug. A film is then formed over portions of the substrate adjacent the sacrificial plug. The sacrificial plug is then selectively removed leaving an opening in the film, and a gate electrode is formed in the opening. The sacrificial plug can be formed from several materials including, for example, polysilicon and nitrogen-bearing species such as nitride. The gate electrode may, for example, be formed from temperature-sensitive metals such as copper since the gate electrode may be formed subsequent to high temperature steps of the fabrication, such as a source drain anneal, for example.
摘要翻译：半导体器件通过在衬底上形成牺牲插塞并在邻近牺牲插塞的衬底中形成有源区而形成。然后在与牺牲插塞相邻的衬底的部分上形成膜。然后选择性地去除牺牲塞，在膜中留下开口，并且在开口中形成栅电极。牺牲塞可以由几种材料形成，包括例如多晶硅和含氮物质如氮化物。栅电极可以例如由诸如铜的温度敏感金属形成，因为栅电极可以在制造的高温步骤（例如源极漏极退火）之后形成。

26. 发明授权

US6020232A Process of fabricating transistors having source and drain regions laterally displaced from the transistors gate 失效
标题翻译：制造具有从晶体管栅极横向移位的源极和漏极区域的晶体管的工艺
公开(公告)号：US6020232A
公开(公告)日：2000-02-01
申请号：US759858
申请日：1996-12-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823468
摘要： An integrated circuit comprising a semiconductor substrate, a gate dielectric formed on an upper surface of the semiconductor substrate, a first and a second conductive gate formed on the gate dielectric, a lightly doped impurity distribution, a first source impurity distribution, and a detached impurity distribution. The first conductive gate is displaced over a first transistor region of the semiconductor substrate and the second transistor gate is displaced over a second transistor region of the semiconductor substrate. The lightly doped impurity distribution is substantially contained within first and second lightly doped impurity regions laterally displaced on either side of a channel region of the second transistor region. A lateral dimension of the channel region of the second transistor region is approximately equal to a lateral dimension of the second conductive gate. The first source impurity distribution is substantially contained within a first source region of the first transistor region. A channel boundary of the first source region is approximately coincident with a lateral position of the second sidewall of the first conductive gate. The detached impurity distribution is substantially contained within first and second pairs of detached source/drain regions. Respective pairs of the detached source/drain regions are laterally displaced on either side of channel regions within corresponding transistor regions. Interior boundaries of the detached source/drain regions are laterally displaced a source/drain displacement from respective sidewalls of the conductive gate. A lateral dimension of the spacer structures is approximately equal to the source/drain displacement.
摘要翻译：一种集成电路，包括半导体衬底，形成在半导体衬底的上表面上的栅极电介质，形成在栅极电介质上的第一和第二导电栅极，轻掺杂杂质分布，第一源杂质分布和分离杂质分配。第一导电栅极位于半导体衬底的第一晶体管区域上，并且第二晶体管栅极位于半导体衬底的第二晶体管区域上。轻掺杂杂质分布基本上包含在在第二晶体管区域的沟道区域的任一侧上横向移位的第一和第二轻掺杂杂质区域内。第二晶体管区域的沟道区域的横向尺寸近似等于第二导电栅极的横向尺寸。第一源杂质分布基本上包含在第一晶体管区域的第一源极区内。第一源极区域的沟道边界与第一导电栅极的第二侧壁的横向位置大致重合。分离的杂质分布基本上包含在第一和第二对分离的源极/漏极区域内。分离的源极/漏极区域的相对对在相应的晶体管区域内的沟道区域的任一侧上横向移位。分离的源极/漏极区域的内部边界横向移位从导电栅极的相应侧壁的源极/漏极位移。间隔结构的横向尺寸近似等于源极/漏极位移。

27. 发明授权

US6017802A Ultra-short transistor fabrication scheme for enhanced reliability 有权
标题翻译：超短晶体管制造方案，提高可靠性
公开(公告)号：US6017802A
公开(公告)日：2000-01-25
申请号：US176605
申请日：1998-10-21
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823425 , H01L21/823468 , H01L29/6656 , H01L29/7835 , Y10S257/90
摘要： A detached drain transistor including a semiconductor substrate, a gate dielectric formed on an upper surface of the substrate, a conductive gate formed on the gate dielectric, a first pair of spacer structures, a first source impurity distribution, a second air of spacer structures, and a drain impurity distribution. The conductive gate is laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between a first source region of the semiconductor substrate and a detached drain region of the semiconductor substrate. A channel boundary of the detached region is laterally displaced from a first sidewall of the conductive gate by a drain displacement. A channel boundary of the first source region is laterally displaced from a second sidewall of the conductive gate by a source displacement. The first pair of spacer structures is formed in contact with the first and second sidewalls of the conductive gate. A lateral dimension of the first pair of spacer structures is approximately equal to the source displacement. The second pair of spacer structures is formed on exterior sidewalls of the first pair of spacer structures such that exterior sidewalls of the second pair of spacer structures are displaced from respective sidewalls of the conductive gate by approximately said drain displacement. In a presently preferred embodiment, the source displacement is approximately 50 to 400 angstroms while the drain displacement is approximately 500 to 1500 angstroms.
摘要翻译：分离的漏极晶体管，包括半导体衬底，形成在衬底的上表面上的栅极电介质，形成在栅极电介质上的导电栅极，第一对间隔结构，第一源杂质分布，间隔结构的第二空气，和漏极杂质分布。导电栅极横向设置在半导体衬底的沟道区域上方。沟道区域横向延伸在半导体衬底的第一源极区域和半导体衬底的分离的漏极区域之间。分离区域的通道边界通过排水位移从导电浇口的第一侧壁横向移位。第一源极区的沟道边界通过源极位移从导电栅极的第二侧壁横向移位。第一对间隔结构形成为与导电栅极的第一和第二侧壁接触。第一对间隔结构的横向尺寸近似等于源位移。第二对间隔结构形成在第一对间隔结构的外侧壁上，使得第二对间隔结构的外侧壁通过大致所述排水位移从导电栅极的相应侧壁位移。在当前优选的实施例中，源位移为大约50至400埃，而排水位移为约500至1500埃。

28. 发明授权

US5998288A Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate 失效
标题翻译：在衬底上表面凹陷的栅极导体的横向附近形成超薄间隔物
公开(公告)号：US5998288A
公开(公告)日：1999-12-07
申请号：US62095
申请日：1998-04-17
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66621 , H01L29/665 , H01L29/7834
摘要： An integrated circuit fabrication process is provided for forming relatively thin sidewall spacers extending laterally from upper portions of opposed sidewall surfaces of a transistor gate conductor which resides partially within a trench of a semiconductor substrate. The present invention contemplates etching a trench through a masking layer and partially through a silicon-based substrate arranged underneath the masking layer. A gate dielectric is then formed upon silicon-based surfaces which border the trench. A conformal dielectric layer is deposited across the masking layer and the gate dielectric, followed by the deposition of a gate conductor material across the dielectric layer. The gate conductor material and the dielectric layer are removed from above the upper surface of the masking layer. Portions of the dielectric layer interposed between the masking layer and the gate conductor are etched to a level commensurate with the substrate surface. An LDD implant self-aligned to the lateral boundaries of the masking layer and the gate conductor sidewall surfaces is forwarded into the substrate underneath the trench. Relatively thin oxide spacer structures are then thermally grown upon the sidewall surfaces of the gate conductor. After removing the masking layer, a source/drain implant is performed. In another embodiment, the gate conductor is formed between the opposed lateral boundaries of the masking layer upon the gate dielectric. A source/drain implant is performed after removing the masking. Relatively thin dielectric spacers are formed upon the upper portions of the sidewall surfaces of the gate conductor by depositing and anisotropically etching a dielectric.
摘要翻译：提供了集成电路制造工艺，用于形成相对薄的侧壁间隔件，其侧向地从位于半导体衬底的沟槽内的晶体管栅极导体的相对的侧壁表面的上部横向延伸。本发明考虑通过掩模层蚀刻沟槽，并部分地穿过布置在掩模层下方的硅基衬底。然后在与沟槽接合的硅基表面上形成栅极电介质。在掩模层和栅极电介质之间沉积保形介电层，随后在电介质层上沉积栅极导体材料。栅极导体材料和电介质层从掩蔽层的上表面上方去除。插入在掩模层和栅极导体之间的电介质层的部分被蚀刻到与衬底表面相当的水平。与屏蔽层和栅极导体侧壁表面的横向边界自对准的LDD注入被转移到沟槽下方的衬底中。然后将相对薄的氧化物间隔物结构热生长在栅极导体的侧壁表面上。在去除掩模层之后，执行源极/漏极注入。在另一个实施例中，栅极导体形成在栅极电介质上的掩蔽层的相对的横向边界之间。在去除掩模之后执行源极/漏极注入。通过沉积和各向异性蚀刻电介质，在栅极导体的侧壁表面的上部形成相对薄的电介质间隔物。

29. 发明授权

US5981368A Enhanced shallow junction design by polysilicon line width reduction using oxidation with integrated spacer formation 失效
标题翻译：通过使用集成间隔物形成的氧化，通过多晶硅线宽减小的增强的浅结设计
公开(公告)号：US5981368A
公开(公告)日：1999-11-09
申请号：US187027
申请日：1998-11-05
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28105 , H01L21/28123 , H01L29/4966
摘要： A method of forming a transistor includes forming a gate dielectric layer upon a substrate, forming a polysilicon layer upon the gate dielectric layer and then forming a thin nitride layer upon the gate polysilicon layer. The thin nitride layer is then pattern etched to define a nitride cap above a future channel. The gate polysilicon layer and a portion of the silicon substrate below the gate dielectric layer is then doped with arsenic. An optional annealing step then causes some of the arsenic to migrate below the nitride cap. A subsequent oxidation step then causes gate conductor/gate oxide stacks with integrated spacers to be defined below the nitride cap. The oxidation step and optional prior annealing step also cause some arsenic to migrate into the channel to form the LDD regions. The substrate is etched to remove portions of the gate polysilicon layer unprotected by the nitride cap. The remaining gate structures below the nitride cap include spacers and LDD regions are formed about the polysilicon gate conductor with the combined structure having a width of the nitride cap. Accordingly, the channel width has been decreased to a size that is even smaller than the width of the nitride cap.
摘要翻译：形成晶体管的方法包括在衬底上形成栅极电介质层，在栅极介电层上形成多晶硅层，然后在栅极多晶硅层上形成薄的氮化物层。然后对薄氮化物层进行图案蚀刻以在未来通道之上限定氮化物帽。栅极多晶硅层和栅极电介质层下面的硅衬底的一部分然后掺杂砷。任选的退火步骤然后使一些砷迁移到氮化物盖下方。随后的氧化步骤然后使得具有集成间隔物的栅极导体/栅极氧化物堆叠被限定在氮化物盖的下方。氧化步骤和可选的先前退火步骤还使一些砷迁移到通道中以形成LDD区域。蚀刻衬底以除去未被氮化物帽保护的栅极多晶硅层的部分。在氮化物盖下面的剩余栅极结构包括间隔物，并且LDD区围绕多晶硅栅极导体形成，其组合结构具有氮化物盖的宽度。因此，通道宽度已经减小到比氮化物盖的宽度更小的尺寸。

30. 发明授权

US5970354A Poly recessed fabrication method for defining high performance MOSFETS 失效
标题翻译：用于定义高性能MOSFET的多凹陷制造方法
公开(公告)号：US5970354A
公开(公告)日：1999-10-19
申请号：US987117
申请日：1997-12-08
申请人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28123
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. An oxide layer is formed over the implanted portion of the polysilicon layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译：提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。栅极的长度可以通过使用间隔物来调节。该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。优选地，在掩模层中形成开口，该开口限定栅极导体的位置。开口的宽度可以通过使用间隔物变窄。由开口限定的多晶硅层的一部分注入n型杂质。在多晶硅层的注入部分上形成氧化物层。蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。随后在栅极导体附近形成LDD区域和源极/漏极区域。

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