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21. 发明申请

US20090225775A1 Serial Buffer To Support Reliable Connection Between Rapid I/O End-Point And FPGA Lite-Weight Protocols 审中-公开
标题翻译：串行缓冲器支持快速I / O端点与FPGA Lite权重协议之间的可靠连接
公开(公告)号：US20090225775A1
公开(公告)日：2009-09-10
申请号：US12043934
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： H04J3/22
CPC分类号： H04L47/30 , H04L49/90 , H04L69/08
摘要： A serial buffer includes a first port configured to implement an serial rapid I/O (sRIO) protocol and a second port configured to implement a Lite-weight serial (Lite) protocol. SRIO packets received on the first port are translated into Lite request packets compatible with the Lite protocol. The Lite request packets are transmitted to the second port. Lite response packets compatible with the Lite protocol are returned to the second port in response to the Lite request packets. The Lite response packets are translated into sRIO response packets compatible with the sRIO protocol. These sRIO response packets are returned to the first port, thereby providing a mechanism to acknowledge successful transmissions from the first port to the second port. Unsuccessful transmissions are identified by a timeout mechanism. The serial buffer also enables transfers from the second port to the first port in a similar manner.
摘要翻译：串行缓冲器包括被配置为实现串行快速I / O（sRIO）协议的第一端口和被配置为实现Lite-weight串行（Lite）协议）的第二端口。在第一个端口接收到的SRIO数据包被转换成与Lite协议兼容的Lite请求报文。 Lite请求数据包被传输到第二个端口。与Lite协议兼容的Lite响应报文将返回到第二个端口，以响应Lite请求报文。 Lite响应数据包被转换为与sRIO协议兼容的sRIO响应数据包。这些sRIO响应分组被返回到第一端口，从而提供一种机制来确认从第一端口到第二端口的成功传输。不成功的传输通过超时机制来识别。串行缓冲器还能够以类似的方式从第二端口传输到第一端口。

22. 发明申请

US20080209089A1 Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor Port 审中-公开
标题翻译：具有并行处理器端口的串行缓冲器的基于分组的并行接口协议
公开(公告)号：US20080209089A1
公开(公告)日：2008-08-28
申请号：US11679813
申请日：2007-02-27
申请人： Jason Z. Mo , Stanley Hronik
发明人： Jason Z. Mo , Stanley Hronik
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A serial buffer is provided having a parallel port configured to couple the serial buffer to a first system via a parallel interface protocol. The serial buffer also includes a serial port configured to couple the serial buffer to a second system via a serial interface protocol and control logic that enables data to be transferred between the parallel port and the serial port in an efficient manner. In one embodiment, the parallel interface protocol is substantially identical to a quad-data rate burst of two (QDRII-B2) interface protocol.
摘要翻译：提供了串行缓冲器，其具有被配置为经由并行接口协议将串行缓冲器耦合到第一系统的并行端口。串行缓冲器还包括串行端口，其配置为通过串行接口协议和控制逻辑将串行缓冲器耦合到第二系统，使得能够以有效的方式在并行端口和串行端口之间传输数据。在一个实施例中，并行接口协议基本上与两个（QDRII-B2）接口协议的四元数据速率突发相同。

23. 发明授权

US08312241B2 Serial buffer to support request packets with out of order response packets 有权
标题翻译：串行缓冲器支持无序响应数据包的请求数据包
公开(公告)号：US08312241B2
公开(公告)日：2012-11-13
申请号：US12043943
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： G06F12/12
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901 , H04L49/9036
摘要： Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.
摘要翻译：在串行缓冲器中，请求数据包被写入存储器缓冲器的可用存储器块，这些存储器块由空闲缓冲器指针列表标识。当请求数据包被写入存储器块时，存储块从空闲缓冲区指针列表中移除，并被添加到使用的缓冲区指针列表中。读取所使用的缓冲器指针列表中的存储器块，从而从串行缓冲器发送关联的请求包。当从存储器块读取请求数据包时，从使用的缓冲区指针列表中删除存储器块，并将其添加到请求缓冲区指针列表中。如果在超时时段内接收到相应的响应包，则将该存储器块从请求缓冲区指针列表传送到空闲缓冲区指针列表。否则，内存块从请求缓冲区指针列表传输到使用的缓冲区指针列表。

24. 发明授权

US08312190B2 Protocol translation in a serial buffer 有权
标题翻译：协议翻译在串行缓冲区
公开(公告)号：US08312190B2
公开(公告)日：2012-11-13
申请号：US12043929
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： G06F3/00 , G06F5/00 , G06F13/12 , G06F13/42 , G06F13/14 , H04L12/56 , H04J3/16
CPC分类号： G06F13/387
摘要： A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.
摘要翻译：串行缓冲器包括被配置为根据第一串行协议操作的第一端口和被配置为根据第二串行协议进行操作的第二端口。串行缓冲器的第一个转换电路允许在第一个端口接收的数据包被转换为第二个串行协议，然后传输到第二个端口。串行缓冲器的第二个转换电路允许在第二个端口上接收到的数据包被转换为第一个串行协议，然后传送到第一个端口。可以响应于包括在所接收的分组的头部中的信息来执行翻译，包括源ID值，目的地ID值和/或病例编号值。

25. 发明授权

US08213448B2 Method to support lossless real time data sampling and processing on rapid I/O end-point 有权
标题翻译：支持快速I / O端点的无损实时数据采样和处理方法
公开(公告)号：US08213448B2
公开(公告)日：2012-07-03
申请号：US12043944
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo , Calvin Nguyen , Bertan Tezcan
发明人： Chi-Lie Wang , Jason Z. Mo , Calvin Nguyen , Bertan Tezcan
IPC分类号： H04L12/54
CPC分类号： H04L1/0082 , H04L47/22 , H04L49/90
摘要： A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.
摘要翻译：串行缓冲器监视传入的数据包流，以识别单个丢失的数据包和多个连续的丢失数据包。在检测到多个连续丢失数据包时，产生中断，从而停止数据传输。在检测到单个丢失的分组时，将单个丢失的分组标识符插入到分组的分组报头中，导致单个丢失分组的标识。传入的数据包，包括任何插入的单个丢失的数据包标识符，被写入队列。当水位达到队列的水位时，读取存储的数据包以创建输出数据包流。当从队列读取的分组包括插入的单个丢失的分组标识符时，将虚拟分组（例如，具有全零的数据有效载荷的分组）插入到输出分组流中。因此，实时应用能够以恒定的方式处理输出分组流。

26. 发明申请

US20090228621A1 Protocol Translation In A Serial Buffer 有权
标题翻译：串行缓冲器中的协议翻译
公开(公告)号：US20090228621A1
公开(公告)日：2009-09-10
申请号：US12043929
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： G06F13/38
CPC分类号： G06F13/387
摘要： A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.
摘要翻译：串行缓冲器包括被配置为根据第一串行协议操作的第一端口和被配置为根据第二串行协议进行操作的第二端口。串行缓冲器的第一个转换电路允许在第一个端口接收的数据包被转换为第二个串行协议，然后传输到第二个端口。串行缓冲器的第二个转换电路允许在第二个端口上接收到的数据包被转换为第一个串行协议，然后传送到第一个端口。可以响应于包括在所接收的分组的头部中的信息来执行翻译，包括源ID值，目的地ID值和/或病例编号值。

27. 发明申请

US20090086750A1 Non-Random Access Rapid I/O Endpoint In A Multi-Processor System 审中-公开
标题翻译：在多处理器系统中的非随机访问快速I / O端点
公开(公告)号：US20090086750A1
公开(公告)日：2009-04-02
申请号：US11863199
申请日：2007-09-27
申请人： Chi-Lie Wang , Jason Z. Mo , Stanley Hronik , Jakob Saxtorph
发明人： Chi-Lie Wang , Jason Z. Mo , Stanley Hronik , Jakob Saxtorph
IPC分类号： H04L12/28
CPC分类号： G06F13/4278
摘要： A system and method for using a doorbell command to allow sRIO devices to operate as bus masters to retrieve data packets stored in a serial buffer, without requiring the SRIO devices to specify the sizes of the data packets. The serial buffer includes a plurality of queues that store data packets. A doorbell frame request packet identifies the queue to be accessed within the serial buffer, but does not specify the size of the data packet(s) to be retrieved. Upon detecting a doorbell frame request packet, the serial buffer operates as a bus master to transfer the requested data packets out of the selected queue. The selected queue can be configured to operate in a flush mode or a non-flush mode. The serial buffer may also indicate that a received doorbell frame request has attempted to access an empty queue.
摘要翻译：一种使用门铃命令来允许sRIO设备作为总线主机操作以检索存储在串行缓冲器中的数据分组的系统和方法，而不需要SRIO设备指定数据分组的大小。串行缓冲器包括存储数据分组的多个队列。门铃帧请求包标识要在串行缓冲器内访问的队列，但不指定要检索的数据包的大小。当检测到门铃帧请求分组时，串行缓冲器作为总线主机操作，以将所请求的数据分组传送出所选择的队列。所选择的队列可以配置为以冲洗模式或非冲洗模式运行。串行缓冲器还可以指示所接收的门铃帧请求尝试访问空队列。

28. 发明申请

US20080209139A1 Rapid Input/Output Doorbell Coalescing To minimize CPU Utilization And Reduce System Interrupt Latency 有权
标题翻译：快速输入/输出门铃聚结以最大限度地减少CPU利用率并减少系统中断延迟
公开(公告)号：US20080209139A1
公开(公告)日：2008-08-28
申请号：US11679823
申请日：2007-02-27
申请人： Chi-Lie Wang , Kwong Hou Mak , Jason Z. Mo
发明人： Chi-Lie Wang , Kwong Hou Mak , Jason Z. Mo
IPC分类号： G06F12/00
CPC分类号： G06F9/30094
摘要： Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.
摘要翻译：使用门铃系统实现状态/错误报告。多个标志寄存器被包括在诸如串行缓冲器的系统设备上。每个标志寄存器具有对应的地址，并存储多个标志。标志扫描控制器使用标志寄存器地址以预定的优先级顺序访问标志寄存器。在检测到标志寄存器的一个或多个标志被激活时，标志扫描控制器产生门铃命令。门铃命令包括标志寄存器地址和相应的标志。系统处理器接收门铃命令并服务激活的标志。一旦激活的标志被服务，系统处理器执行一个或多个软件写入操作来清除系统设备内的标志。系统处理器可以同时维护多个标志。系统处理器还可以同时清除多个标志。

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