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21. 发明申请

US20100052121A1 SEMICONDUCTOR SYSTEM-IN-A-PACKAGE CONTAINING MICRO-LAYERED LEAD FRAME 有权
标题翻译：包含微层引线框架的半导体系统级封装
公开(公告)号：US20100052121A1
公开(公告)日：2010-03-04
申请号：US12334267
申请日：2008-12-12
申请人： Manolito Galera , Leocadio Morona Alabin
发明人： Manolito Galera , Leocadio Morona Alabin
IPC分类号： H01L23/538 , H01L21/98
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/49541 , H01L23/49568 , H01L23/49589 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/50 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/48247 , H01L2224/49171 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.
摘要翻译：描述了包含系统级封装的半导体封装以及制造这种封装的方法。所述半导体封装包含位于焊盘阵列的中间的第一半导体管芯，设置在所述第一管芯上方的第二管芯并且搁置在连接到焊盘阵列的布线引线上，第三管芯沉积在第二裸片的背面上通过引线接合并连接到焊盘阵列，以及置于器件焊盘上的无源器件和/或分立器件。封装还包含作为散热器工作的热焊盘。通过蚀刻引线框形成焊盘阵列。半导体封装具有薄封装尺寸的完整焊盘阵列，同时具有系统级封装设计。还描述了其它实施例。

22. 发明申请

US20110163428A1 SEMICONDUCTOR PACKAGES WITH EMBEDDED HEAT SINK 审中-公开
标题翻译：半导体封装与嵌入式散热器
公开(公告)号：US20110163428A1
公开(公告)日：2011-07-07
申请号：US12652491
申请日：2010-01-05
申请人： Manolito Fabres Galera , Leocadio Morona Alabin , In Suk Kim
发明人： Manolito Fabres Galera , Leocadio Morona Alabin , In Suk Kim
IPC分类号： H01L23/495
CPC分类号： H01L23/49568 , H01L23/3677 , H01L23/49827 , H01L2224/16245 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
摘要： Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a leadframe having an array of holes with a layout corresponding to the land pad array of the package, wherein the holes contain a thermally-conductive dielectric material with a via therein containing an electrically conductive material. The electrically conductive materials can extend past the bottom of the leadframe to form the land pad array of the packages. With such a configuration, the leadframe can act as an embedded heat sink in the package and there is no need to mount an additional heat sink to the package for thermal dissipation, allowing a thinner package to be manufactured. With such a configuration, the semiconductor packages have a full land pad array, providing a smaller footprint and a higher I/O capacity. Other embodiments are also described.
摘要翻译：描述了半导体封装及其制造和使用方法。半导体封装包含具有阵列阵列的引线框架，其具有对应于封装的焊盘阵列的布局，其中所述孔包含导热介电材料，其中通孔中含有导电材料。导电材料可延伸穿过引线框架的底部以形成封装的焊盘阵列。通过这样的配置，引线框架可以作为封装中的嵌入式散热器，并且不需要将额外的散热器安装到封装件上用于散热，从而允许制造更薄的封装。通过这种配置，半导体封装具有完整的焊盘阵列，提供更小的占用面积和更高的I / O容量。还描述了其它实施例。

23. 发明申请

US20100244211A1 MULTICHIP DISCRETE PACKAGE 有权
标题翻译： MULTICHIP分离包装
公开(公告)号：US20100244211A1
公开(公告)日：2010-09-30
申请号：US12409620
申请日：2009-03-24
申请人： Manolito Fabres Galera , Leocadio Morona Alabin
发明人： Manolito Fabres Galera , Leocadio Morona Alabin
IPC分类号： H01L23/52 , H01L21/98
CPC分类号： H01L23/49575 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48472 , H01L2224/49171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs.
摘要翻译：一种具有引线框架的多芯片分立封装，其具有多个引线和第一管芯附着焊盘（DAP），所述第一DAP具有在所述第一DAP上方延伸的侧部，与所述第一DAP结合的第一分立管芯，至少第一引线接合其形成第一离散模具和多个引线中的第一选定一个引线之间的电连接，附接到形成第二DAP的侧部的顶部的金属板，结合到第二DAP的第二分立模具，至少第二引线键合，其形成第二离散管芯和第二选定引线之间的电连接; 以及围绕第一和第二管芯以及第一和第二DAP形成的封装材料。

24. 发明申请

US20100140773A1 STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：堆叠芯片，微层导线框架半导体封装
公开(公告)号：US20100140773A1
公开(公告)日：2010-06-10
申请号：US12332207
申请日：2008-12-10
申请人： Manolito Fabres Galera , Leocadio Morona Alabin
发明人： Manolito Fabres Galera , Leocadio Morona Alabin
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： H01L25/50 , H01L21/4832 , H01L23/3107 , H01L23/315 , H01L23/49517 , H01L23/49541 , H01L23/49575 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/16 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Semiconductor packages that contain stacked chips on a micro-layered lead frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full array of land pads that has been formed from a lead frame. The packages comprise multiple chips that are stacked vertically and separated by routing leads which are connected to the land pad array. The routing leads can be etched from a metal cladding layer that is provided between each set of stacked chips. Each chip and its routing leads can be encapsulated before the next chip is provided in the package. The semiconductor packages therefore have a high input/output capability with a small package footprint, a flexible routing capability, and a small thickness for multiple chips that are stacked in the package. Other embodiments are also described.
摘要翻译：描述了在微层引线框架上包含堆叠芯片的半导体封装以及制造这种半导体封装的方法。半导体封装包含从引线框架形成的全部阵列焊盘。这些包装件包括垂直堆叠并通过连接到焊盘阵列的布线引线分开的多个芯片。可以从设置在每组堆叠芯片之间的金属包覆层来蚀刻布线引线。每个芯片及其路由引线可以在封装中提供下一个芯片之前进行封装。因此，半导体封装具有高的输入/输出能力，具有小的封装占地面积，灵活的布线能力，以及堆叠在封装中的多个芯片的小厚度。还描述了其它实施例。

25. 发明授权

US08314480B2 Stackable semiconductor package with embedded die in pre-molded carrier frame 有权
标题翻译：具有嵌入式模具的可堆叠半导体封装在预成型载体框架中
公开(公告)号：US08314480B2
公开(公告)日：2012-11-20
申请号：US12701773
申请日：2010-02-08
申请人： Manolito Fabres Galera , Leocadio Morona Alabin , In Suk Kim
发明人： Manolito Fabres Galera , Leocadio Morona Alabin , In Suk Kim
IPC分类号： H01L23/02
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3107 , H01L23/49517 , H01L2224/16245 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
摘要： Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability that are especially useful for portable and ultra-portable electronic apparatus. Other embodiments are also described.
摘要翻译：描述了包含嵌入在预模制载体框架中的多个堆叠芯片的半导体封装以及用于制造这种半导体封装的方法。半导体封装包含一个完整的焊盘阵列和垂直堆叠的多个芯片。焊盘阵列包含由位于下模上的第一凸块凸起形成的内部端子。焊盘阵列还包含在嵌入第一裸片的第一模制层中由第一导电通孔形成的中间端子。第一导电通孔连接到位于第二模具上的第二凸块凸块，该第二模具嵌入在第二模制层中。第二成型层包含连接到载体框架的第二导电通孔，其底部形成焊盘阵列的外部端子。因此，半导体封装具有高的输入/输出能力，具有小的封装占地面积，以及对便携式和超便携式电子设备特别有用的灵活布线能力。还描述了其它实施例。

26. 发明申请

US20110193206A1 STACKABLE SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE IN PRE-MOLDED CARRIER FRAME 有权
标题翻译：具有嵌入式模块的载体框架的可堆叠半导体封装
公开(公告)号：US20110193206A1
公开(公告)日：2011-08-11
申请号：US12701773
申请日：2010-02-08
申请人： Manolito Fabres Galera , Leocadio Morona Alabin , In Suk Kim
发明人： Manolito Fabres Galera , Leocadio Morona Alabin , In Suk Kim
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L21/568 , H01L23/3107 , H01L23/49517 , H01L2224/16245 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
摘要： Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability that are especially useful for portable and ultra-portable electronic apparatus. Other embodiments are also described.
摘要翻译：描述了包含嵌入在预模制载体框架中的多个堆叠芯片的半导体封装以及用于制造这种半导体封装的方法。半导体封装包含一个完整的焊盘阵列和垂直堆叠的多个芯片。焊盘阵列包含由位于下模上的第一凸块凸起形成的内部端子。焊盘阵列还包含在嵌入第一裸片的第一模制层中由第一导电通孔形成的中间端子。第一导电通孔连接到位于第二模具上的第二凸块凸块，该第二模具嵌入在第二模制层中。第二成型层包含连接到载体框架的第二导电通孔，其底部形成焊盘阵列的外部端子。因此，半导体封装具有高的输入/输出能力，具有小的封装占地面积，以及对便携式和超便携式电子设备特别有用的灵活布线能力。还描述了其它实施例。

27. 发明申请

US20100181660A1 Multi-Chip Semiconductor Package 有权
标题翻译：多芯片半导体封装
公开(公告)号：US20100181660A1
公开(公告)日：2010-07-22
申请号：US12356354
申请日：2009-01-20
申请人： Monolito Galera , Leocadio Morona Alabin
发明人： Monolito Galera , Leocadio Morona Alabin
IPC分类号： H01L25/11 , H01L21/50
CPC分类号： H01L23/49541 , H01L23/3107 , H01L23/4951 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/04042 , H01L2224/05001 , H01L2224/05023 , H01L2224/05111 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/16 , H01L2224/32145 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2225/0651 , H01L2225/06517 , H01L2225/06582 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/013 , H01L2924/00012 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755
摘要： Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.
摘要翻译：描述了包含多个堆叠芯片的半导体封装以及用于制造这种半导体封装的方法。半导体封装包含一个完整的焊盘阵列和垂直堆叠的多个芯片。一些芯片被连接到焊盘阵列的路由引线分开。芯片可以直接连接到焊盘阵列的内部，并且第二和第三芯片分别通过连接到焊球的布线引线连接到焊盘阵列的中部和外部部分。因此，半导体封装具有高的输入/输出能力，具有小的封装占地面积和灵活的布线能力。还描述了其它实施例。

28. 发明授权

US08268671B2 Semiconductor system-in-package and methods for making the same 有权
标题翻译：半导体系统级封装及其制造方法
公开(公告)号：US08268671B2
公开(公告)日：2012-09-18
申请号：US13019751
申请日：2011-02-02
申请人： Monolito Fabres Galera , Leocadio Morona Alabin
发明人： Monolito Fabres Galera , Leocadio Morona Alabin
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L23/49537 , H01L21/568 , H01L23/3121 , H01L23/4951 , H01L23/49572 , H01L23/49575 , H01L23/49589 , H01L24/48 , H01L2224/05554 , H01L2224/16 , H01L2224/48247 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.
摘要翻译：描述了包含系统的半导体器件以及用于制造这种封装的方法。具有封装系统（SIP）的半导体器件包含包含在封装的较低级中的第一IC裸片，无源元件和分立器件。 SIP还包含通过金属插入件的阵列与第一IC管芯垂直分离的第二IC管芯，从而将第一IC管芯的部件与第二IC管芯的部件隔离。这种配置在单个半导体封装内提供更多功能，同时还减少或消除封装中的局部加热。还描述了其它实施例。

29. 发明授权

US07977776B2 Multichip discrete package 有权
标题翻译：多芯离散封装
公开(公告)号：US07977776B2
公开(公告)日：2011-07-12
申请号：US12409620
申请日：2009-03-24
申请人： Manolito Fabres Galera , Leocadio Morona Alabin
发明人： Manolito Fabres Galera , Leocadio Morona Alabin
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48472 , H01L2224/49171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/1305 , H01L2924/13091 , H01L2924/19107 , H01L2924/00014 , H01L2924/00
摘要： A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs.
摘要翻译：一种具有引线框架的多芯片分立封装，其具有多个引线和第一管芯附着焊盘（DAP），所述第一DAP具有在所述第一DAP上方延伸的侧部，与所述第一DAP结合的第一分立管芯，至少第一引线接合其形成第一离散模具和多个引线中的第一选定一个引线之间的电连接，附接到形成第二DAP的侧部的顶部的金属板，结合到第二DAP的第二分立模具，至少第二引线键合，其形成第二离散管芯和第二选定引线之间的电连接; 以及围绕第一和第二管芯以及第一和第二DAP形成的封装材料。

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