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21. 发明授权

US08812843B2 Device and authentication method therefor 有权
标题翻译：设备及认证方法
公开(公告)号：US08812843B2
公开(公告)日：2014-08-19
申请号：US13524843
申请日：2012-06-15
申请人： Yuji Nagai , Taku Kato , Tatsuyuki Matsushita , Toshihiro Suzuki , Noboru Shibata
发明人： Yuji Nagai , Taku Kato , Tatsuyuki Matsushita , Toshihiro Suzuki , Noboru Shibata
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes first and second data generator, a one-way function processor, and a data output interface. The first data generator generates a second key by encrypting a host constant with a first key in AES operation. The second data generator generates a session key by encrypting a random number with a second key in AES operation. The one-way function processor generates authentication information by processing secret identification information with the session key in one-way function operation. The data output interface outputs the encrypted secret identification information, a family key block, and the authentication information to outside of the device.
摘要翻译：根据一个实施例，设备包括第一和第二数据生成器，单向功能处理器和数据输出接口。第一个数据生成器通过AES操作中的第一个密钥加密主机常数来生成第二个密钥。第二数据生成器通过在AES操作中用第二密钥加密随机数生成会话密钥。单向功能处理器通过在单向功能操作中通过会话密钥处理秘密识别信息来生成认证信息。数据输出接口将加密的秘密识别信息，家庭密钥块和认证信息输出到设备外部。

22. 发明授权

US08732466B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08732466B2
公开(公告)日：2014-05-20
申请号：US13524894
申请日：2012-06-15
申请人： Yuji Nagai , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
发明人： Yuji Nagai , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes a first memory area to store a first key. A second memory area stores encrypted secret identification (ID) information generated from secret ID information with a family key. A third memory area stores a family key block including data generated from the family key with an ID key. An authentication module performs authentication. A second key is generated from a first number with the first key, a session key is generated from a random number with the second key, and authentication information is generated from the secret ID information with the session key. The encrypted secret ID information, family key block and the authentication information is output.
摘要翻译：根据一个实施例，设备包括用于存储第一密钥的第一存储区域。第二存储区域存储从秘密ID信息生成的加密的秘密标识（ID）信息与家庭密钥。第三存储区域存储包括具有ID密钥的家族密钥产生的数据的家庭密钥块。认证模块执行认证。从具有第一密钥的第一号码生成第二密钥，从具有第二密钥的随机数生成会话密钥，并且从具有会话密钥的秘密ID信息生成认证信息。输出加密的秘密ID信息，家庭密钥块和认证信息。

23. 发明授权

US08687420B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08687420B2
公开(公告)日：2014-04-01
申请号：US13589842
申请日：2012-08-20
申请人： Noboru Shibata , Kazunori Kanebako
发明人： Noboru Shibata , Kazunori Kanebako
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C29/00 , G11C2211/5642 , G11C2211/5648
摘要： A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i
摘要翻译：一种半导体存储器件，包括存储多位数据的多位存储器单元和存储少位数据以及多位数据的数据的存储器单元。因此，半导体存储器件包括用于存储一个单元的n位（其中n是等于或大于2的自然数）的多个存储器单元。在多个存储单元中，h位（h＆nlE; n）数据被存储在第一区域MLB的存储器MLC中，i位（i

24. 发明申请

US20130145083A1 Semiconductor Memory Device 有权
标题翻译：半导体存储器件
公开(公告)号：US20130145083A1
公开(公告)日：2013-06-06
申请号：US13690961
申请日：2012-11-30
申请人： Toshihiro Suzuki , Noboru Shibata , Takahiro Shimizu
发明人： Toshihiro Suzuki , Noboru Shibata , Takahiro Shimizu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/1433 , G06F21/79
摘要： According to one embodiment, a semiconductor memory device includes a memory which comprises an area accessible from outside and a confidential information area storing confidential information and a set flag. A controller reads the flag from the memory when instructed to erase data in the confidential information area, determines whether the flag is set, erases data in the confidential information area when the flag is clear, and abandons process requested by the data erase instruction when the flag is set. An authenticator uses data in the confidential information area to execute operation for authentication.
摘要翻译：根据一个实施例，半导体存储器件包括存储器，其包括可从外部访问的区域和存储机密信息的机密信息区域和设置标志。当指示擦除机密信息区域中的数据时，控制器从存储器读取标志，确定标志是否被置位，当标志清除时，擦除机密信息区域中的数据，并且当数据擦除指令被请求时放弃由数据擦除指令请求的处理标志设置。验证者使用机密信息区域中的数据来执行认证操作。

25. 发明申请

US20130142325A1 MEMORY 有权
标题翻译：记忆
公开(公告)号：US20130142325A1
公开(公告)日：2013-06-06
申请号：US13524873
申请日：2012-06-15
申请人： Yuji NAGAI , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
发明人： Yuji NAGAI , Toshihiro Suzuki , Noboru Shibata , Taku Kato , Tatsuyuki Matsushita
IPC分类号： H04L9/28
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/0021 , G11B20/00217 , G11B20/00253 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a memory includes a first storage region capable of storing first key (NKey) information, and secret identification information (SecretID) unique to the authenticate, reading and writing data from and to the first storage region from an outside of the authenticatee being inhibited at least after the authenticatee is shipped.
摘要翻译：根据一个实施例，存储器包括能够存储第一密钥（NKey）信息的第一存储区域和从第一存储区域的外部识别，读取和写入数据的唯一的秘密识别信息（SecretID）至少在验证者发货后，验证者被禁止。

26. 发明授权

US08284607B2 Semiconductor memory system including a plurality of semiconductor memory devices 有权
标题翻译：半导体存储器系统包括多个半导体存储器件
公开(公告)号：US08284607B2
公开(公告)日：2012-10-09
申请号：US12645104
申请日：2009-12-22
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
摘要翻译：通信线路连接到第一和第二芯片，并保持在第一信号电平。监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制为等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

27. 发明授权

US08279670B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08279670B2
公开(公告)日：2012-10-02
申请号：US12882507
申请日：2010-09-15
申请人： Takuya Futatsuyama , Yoshihisa Kondo , Noboru Shibata
发明人： Takuya Futatsuyama , Yoshihisa Kondo , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C8/00 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.
摘要翻译：根据实施例的非易失性半导体存储装置包括：包括电可重写存储器单元阵列的存储单元阵列，并且被配置为能够将N位数据（其中N是不小于2的自然数）存储在一个记忆体; 以及控制器，用于控制存储单元阵列的读，写和擦除操作。存储单元阵列包括具有第一存储器单元的第一区域，该第一存储器单元可操作以保留N位数据，以及具有第二存储单元的第二区域，该第二存储单元可操作以保持M位数据（其中M是小于N的自然数）。当访问第一存储器单元时，由控制器接收的地址数据的数据结构与在访问第二存储单元时从外部接收的地址数据的数据结构相同。

28. 发明申请

US20120163091A1 SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL 有权
标题翻译：存储细胞中的数据的半导体存储器件
公开(公告)号：US20120163091A1
公开(公告)日：2012-06-28
申请号：US13413779
申请日：2012-03-07
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k
摘要翻译：存储单元阵列被配置为具有以矩阵形式布置的多个存储单元，每个存储单元连接到字线和位线，并且能够存储n个值（n是等于或大于其的自然数）比3）。控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。控制电路在写入操作中将数据写入存储单元中的k值阈值电压（k <= n），对位线进行一次预充电，然后改变字线的电位i次，以验证是否存储器单元已达到i值（i <= k）阈值电压。

29. 发明申请

US20120044764A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION 有权
标题翻译：执行擦除操作的非易失性半导体存储器件
公开(公告)号：US20120044764A1
公开(公告)日：2012-02-23
申请号：US13052158
申请日：2011-03-21
申请人： Jun NAKAI , Noboru Shibata
发明人： Jun NAKAI , Noboru Shibata
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16 , G11C16/14 , G11C16/26 , G11C16/344 , G11C16/3445
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制单元。存储单元阵列包括以矩阵形式布置的多个存储单元。控制单元擦除存储单元的数据。控制单元在擦除操作期间根据第一命令中断存储器单元的擦除操作并保持中断前的擦除条件，并且根据第二命令基于保持的擦除条件恢复擦除操作。

30. 发明授权

US08098524B2 Semiconductor memory device capable of increasing writing speed 有权
标题翻译：能够提高写入速度的半导体存储器件
公开(公告)号：US08098524B2
公开(公告)日：2012-01-17
申请号：US13072240
申请日：2011-03-25
申请人： Noboru Shibata , Kenichi Imamiya
发明人： Noboru Shibata , Kenichi Imamiya
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C11/5628 , G11C16/0483 , G11C16/30
摘要： A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.
摘要翻译：存储单元阵列具有这样的结构，其中与字线和位线连接并且串联连接的多个存储单元以矩阵形式布置。选择晶体管选择字线。控制电路根据输入数据控制字线和位线的电位，并且控制数据相对于存储单元的写入，读取和擦除操作。选择晶体管形成在阱上，并且第一负电压被提供给阱，第一电压（第一电压≥第一负电压）被提供给所选择的字线，并且第二电压被提供给非易失性存储器，在读取操作中选择字线。

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