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    • 21. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06711088B2
    • 2004-03-23
    • US10418049
    • 2003-04-18
    • Mitsuaki HayashiShuji NakayaMakoto Kojima
    • Mitsuaki HayashiShuji NakayaMakoto Kojima
    • G11C800
    • G11C7/22G11C8/08G11C17/12G11C2207/2281
    • By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.
    • 通过消除由存储器单元中的泄漏电流规则地产生的位线的电流,使每个位线的存储单元的数量增加,实现存储单元阵列的大的存储容量,以及半导体存储器件 提供了能够减少芯片面积的功能。 为了实现这一点,提供了一种源极线电位控制电路,用于设置包括在存储单元中的晶体管的源极电位,所述晶体管由位于地电位的行选择信号选择,并且用于设置包含在存储器中的晶体管的源极电位 通过处于功率电位的行选择信号将单元设置为非选择状态。 因此,包括在非选择状态的存储单元中的晶体管的源极和漏极之间的电位差被减小,并且消除了漏电流。
    • 23. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US06407946B2
    • 2002-06-18
    • US09731005
    • 2000-12-07
    • Takafumi MaruyamaMakoto Kojima
    • Takafumi MaruyamaMakoto Kojima
    • G11C1606
    • G11C16/28
    • To read data stored on a memory cell transistor with a floating gate, a flash memory uses: a single-gate reference transistor; a differential sense amplifier; and a gate voltage generator for generating a gate voltage for the reference transistor. The gate voltage generator includes: a dummy cell transistor, which has the same structure as the memory cell transistor and has been turned ON; a current mirror for creating a current proportional to a drain current of the dummy cell transistor; an NMOS transistor for generating a gate voltage for the reference transistor in accordance with the current created by the current mirror; and a voltage hold circuit for holding the gate voltage generated. Even if temperature or fabricating process conditions have changed, this construction ensures accurate and high-speed read operation.
    • 为了利用浮动栅极读取存储在存储单元晶体管上的数据,闪存使用:单栅极参考晶体管; 差分读出放大器; 以及用于产生用于参考晶体管的栅极电压的栅极电压发生器。 栅极电压发生器包括:具有与存储单元晶体管相同结构并已导通的虚设单元晶体管; 用于产生与虚设单元晶体管的漏极电流成比例的电流的电流镜; NMOS晶体管,用于根据由电流镜产生的电流产生用于参考晶体管的栅极电压; 以及用于保持所产生的栅极电压的电压保持电路。 即使温度或制造工艺条件发生变化,这种结构确保了准确和高速的读取操作。
    • 24. 发明授权
    • MOS semiconductor integrated circuit having a current mirror
    • MOS半导体集成电路具有电流镜
    • US06229382B1
    • 2001-05-08
    • US09151736
    • 1998-09-11
    • Makoto Kojima
    • Makoto Kojima
    • H03K301
    • G05F3/262H01L29/7835H03F3/345
    • The MOS semiconductor integrated circuit of the present invention includes: a plurality of serial transistors serially and sequentially connected to the drain of an output transistor of a current mirror circuit receiving input current; a plurality of reference voltage transistors, each connected serially between the gate of an associated one of the serial transistors and ground; PMOS transistors each supplying constant current to an associated one of the reference voltage transistors; an input transistor of an output current mirror circuit, which is connected to the drain of one of the serial transistors that is closest to the input transistor of the output current mirror circuit; and an output transistor of the output current mirror circuit for supplying output current.
    • 本发明的MOS半导体集成电路包括:串联并顺序地连接到接收输入电流的电流镜电路的输出晶体管的漏极的多个串联晶体管; 多个参考电压晶体管,每个参考电压晶体管串联连接在相关联的一个串联晶体管的栅极和地之间; 每个PMOS晶体管向参考电压晶体管中的相关一个提供恒定电流; 输出电流镜电路的输入晶体管,其连接到最靠近输出电流镜电路的输入晶体管的一个串联晶体管的漏极; 以及用于提供输出电流的输出电流镜电路的输出晶体管。
    • 30. 发明授权
    • Liquid crystal device
    • 液晶装置
    • US5552193A
    • 1996-09-03
    • US399043
    • 1995-03-06
    • Masanobu AsaokaHideaki TakaoTakeshi ToganoMakoto Kojima
    • Masanobu AsaokaHideaki TakaoTakeshi ToganoMakoto Kojima
    • G02F1/1337
    • G02F1/133723Y10T428/1018Y10T428/1023Y10T428/1027
    • A liquid crystal device is constituted by disposing a liquid crystal between a pair of substrates; at least one of which has thereon an alignment film comprising a polymer selected from Polymers (I)-(III) below:Polymer (I), which is a polymer composite comprising at least two polymer components including a polyamide represented by a structural unit of the following formula (1): ##STR1## wherein R.sub.11 and R.sub.12 independently denote an alkyl group having 1-10 carbon atoms or a fluoroalkyl group having 1-10 carbon atoms;Polymer (II) which is a composite polyamide having at least two species of dicarboxylic acid-originated units each represented by formula (2) below: ##STR2## wherein R.sub.21 denotes a divalent organic residue group including an aromatic ring; and a diamine-originated unit represented by formula (3) below: ##STR3## wherein R.sub.22 and R.sub.23 independently denote an alkyl group having 1-10 carbon atoms, with the proviso that at least one species of the dicarboxylic acid originated units is one having a straight molecular structure; andPolymer (III) which is a polyamide composite comprising at least two polyamides formed from an aromatic ring-containing acid component and a diamine component represented by formula (4) below: ##STR4## wherein R.sub.41 and R.sub.42 independently denote an alkyl group having 1-10 carbon atoms.
    • 液晶装置通过在一对基板之间设置液晶而构成; 其中至少一个具有取向膜,该取向膜包含选自以下的聚合物(I) - (III)的聚合物:聚合物(I),其为包含至少两种聚合物组分的聚合物复合物,所述聚合物组分包括由以下结构单元 下式(1):其中R11和R12独立地表示具有1-10个碳原子的烷基或具有1-10个碳原子的氟代烷基; 聚合物(II),其为具有由下式(2)表示的至少两种二羧酸起始单元的复合聚酰胺:其中R 21表示包含芳环的二价有机残基; 和由下式(3)表示的二胺起始单元:y表示具有1-10个碳原子的烷基,条件是至少一种二羧酸起始单元是具有直链分子结构的单元; 和聚合物(III),其是包含至少两种由含芳环的酸组分形成的聚酰胺和由下式(4)表示的二胺组分的聚酰胺复合物:其中R41和R42独立地表示烷基 具有1-10个碳原子的基团。