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21. 发明申请

US20130346728A1 Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令性能
公开(公告)号：US20130346728A1
公开(公告)日：2013-12-26
申请号：US14012344
申请日：2013-08-28
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

22. 发明申请

US20100138608A1 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor 有权
标题翻译：用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
公开(公告)号：US20100138608A1
公开(公告)日：2010-06-03
申请号：US12317959
申请日：2008-12-31
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除对应于所记录的指令 - 高速缓存方式的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

23. 发明申请

US20090249036A1 EFFICIENT METHOD AND APPARATUS FOR EMPLOYING A MICRO-OP CACHE IN A PROCESSOR 有权
标题翻译：在处理器中使用微型高速缓存的有效方法和设备
公开(公告)号：US20090249036A1
公开(公告)日：2009-10-01
申请号：US12060239
申请日：2008-03-31
申请人： Lihu Rappoport , Robert Valentine , Stephan Jourdan , Franck Sala , Amir Leibovitz , Ido Ouziel , Ron Gabor
发明人： Lihu Rappoport , Robert Valentine , Stephan Jourdan , Franck Sala , Amir Leibovitz , Ido Ouziel , Ron Gabor
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/30145 , G06F9/3802 , G06F9/382 , Y02D10/171
摘要： Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.
摘要翻译：公开了在处理器中使用微操作高速缓存的方法和装置。指令指针的标签匹配检索一组具有匹配标签的微操作高速缓存行访问元组。该集合存储在匹配队列中。来自匹配队列的线路访问元组用于访问微操作高速缓存数据阵列中的高速缓存行以提供微操作队列。在微操作缓存未命中时，宏指令转换引擎（MITE）解码宏指令以提供微操作队列。指令指针存储在从MITE获取宏指令的小队列中。当缺席队列为空时，MITE可能会被禁用以节省电力，而当匹配队列为空时，也可以为微操作高速缓存数据阵列。随后微操作高速缓存未命中的微操作高速缓存中的最后一个微操作中的同步标志指示来自MITE的微操作与微操作高速缓存的微操作合并。

24. 发明申请

US20160179545A1 INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING 审中-公开
标题翻译：基于注册的硬件存储器恢复的指令和逻辑
公开(公告)号：US20160179545A1
公开(公告)日：2016-06-23
申请号：US14581268
申请日：2014-12-23
申请人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
发明人： Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/30043 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3891
摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
摘要翻译：处理器包括核心，存储器子系统，预测器模块和存储器重命名模块。预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑，以及基于所识别的依赖关系将存储器重命名（MRN）寄存器分配给存储指令和加载指令的第二逻辑。此外，存储器重命名模块可以包括第三逻辑，用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。

25. 发明申请

US20140298140A1 APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY 有权
标题翻译：用于实现多层次记忆层次的装置和方法
公开(公告)号：US20140298140A1
公开(公告)日：2014-10-02
申请号：US13994105
申请日：2011-12-22
申请人： Theodros Yigzaw , Oded Lempel , Hisham Hafi , Geeyarpuram N Santhanakrisnan , Jose A Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Yuli Mandelblat
发明人： Theodros Yigzaw , Oded Lempel , Hisham Hafi , Geeyarpuram N Santhanakrisnan , Jose A Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Yuli Mandelblat
IPC分类号： G06F11/10
CPC分类号： G06F11/1064 , G06F11/0793 , G06F11/1016 , G06F11/1407
摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
摘要翻译：描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令获取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

26. 发明授权

US08433850B2 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor 有权
标题翻译：用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
公开(公告)号：US08433850B2
公开(公告)日：2013-04-30
申请号：US12326885
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Ilhyun Kim , Lior Libis , Ron Gabor , Oded Lempel
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Ilhyun Kim , Lior Libis , Ron Gabor , Oded Lempel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除对应于所记录的指令 - 高速缓存方式的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

27. 发明申请

US20100115248A1 Technique for promoting efficient instruction fusion 有权
标题翻译：促进高效指导融合的技术
公开(公告)号：US20100115248A1
公开(公告)日：2010-05-06
申请号：US12290395
申请日：2008-10-30
申请人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
发明人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3017 , G06F9/30196 , G06F9/3836 , G06F12/084 , G06F12/0875 , G06F13/4063 , G06F2212/452 , G06F2212/62 , Y02D10/14 , Y02D10/151
摘要： A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
摘要翻译：一种在计算机系统内实现高效指令融合的技术。在一个实施例中，如果指令队列中的第一指令与第二指令可熔，则处理器逻辑延迟第二指令的处理阈值时间量。

28. 发明申请

US20160378487A1 EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART 审中-公开
公开(公告)号：US20160378487A1
公开(公告)日：2016-12-29
申请号：US15143518
申请日：2016-04-30
申请人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
发明人： Ido Ouziel , Lihu Rappoport , Robert Valentine , Ron Gabor , Pankaj Raghuvanshi
IPC分类号： G06F9/30 , G06F12/0875
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3017 , G06F9/30196 , G06F9/3836 , G06F12/084 , G06F12/0875 , G06F13/4063 , G06F2212/452 , G06F2212/62 , Y02D10/14 , Y02D10/151
摘要： A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

29. 发明申请

US20150169365A1 HYBRID THREADING 有权
标题翻译：混合螺纹
公开(公告)号：US20150169365A1
公开(公告)日：2015-06-18
申请号：US14107149
申请日：2013-12-16
申请人： Alexander Gendler , Lihu Rappoport
发明人： Alexander Gendler , Lihu Rappoport
IPC分类号： G06F9/48 , G06F1/28
CPC分类号： G06F9/5094 , G06F1/324 , G06F1/329 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/22 , Y02D10/24
摘要： Hybrid threading in a processor is described. An integrated circuit that implements hybrid threading includes a power control unit (PCU), a first functional hardware unit coupled to the PCU, and a second functional hardware unit coupled to the PCU. The first functional hardware unit and the second functional hardware unit are heterogeneous functional hardware units. The PCU is configured to monitor at least one power attribute of the first and second functional hardware units. The PCU is further configured to calculate an aggregate power value based on the monitored at least one power attribute. Upon determining that the aggregate power value is below a power threshold, the PCU is also configured to calculate a first frequency for the first functional hardware unit and a second frequency for the second functional hardware unit that results in an updated aggregate power value that is closer to the power threshold.
摘要翻译：描述处理器中的混合线程。实现混合线程的集成电路包括功率控制单元（PCU），耦合到PCU的第一功能硬件单元和耦合到PCU的第二功能硬件单元。第一功能硬件单元和第二功能硬件单元是异构功能硬件单元。 PCU被配置为监视第一和第二功能硬件单元的至少一个功率属性。 PCU还被配置为基于所监视的至少一个功率属性来计算总功率值。在确定总功率值低于功率阈值时，PCU还被配置为计算第一功能硬件单元的第一频率和第二功能硬件单元的第二频率，其导致更接近的更新聚合功率值到功率阈值。

30. 发明授权

US08782374B2 Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor 有权
标题翻译：在处理器的微操作高速缓存中包含TLB条目的方法和装置
公开(公告)号：US08782374B2
公开(公告)日：2014-07-15
申请号：US12326882
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
IPC分类号： G06F12/00 , G06F13/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/0864 , G06F12/0875 , G06F12/1036 , G06F12/1045 , G06F12/126 , G06F2212/652 , Y02D10/13
摘要： Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
摘要翻译：公开了在处理器微操作高速缓存中包含TLB（翻译后备缓冲器）的方法和装置。包含TLB条目的一些实施例具有响应于访问TLB条目设置的微操作高速缓存包含字段。包含逻辑可以刷新微操作高速缓存或微操作高速缓存的部分，并且每当其相关联的包含字段被设置时响应于TLB条目的替换或无效而清除相应的包含字段。前端处理器状态也可以被清除，并且在由TLB未命中引起替换时，指令被重新指定。

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