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21. 发明授权

US08180822B2 Method and system for processing the booth encoding 33RD term 有权
标题翻译： 33RD项目编号处理方法及系统
公开(公告)号：US08180822B2
公开(公告)日：2012-05-15
申请号：US12203644
申请日：2008-09-03
申请人： Leonard D. Rarick
发明人： Leonard D. Rarick
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/5338
摘要： A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result, a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero, and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term. The shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation.
摘要翻译：一种用于计算二进制运算的计算机系统，所述二进制运算涉及第一项乘以产生产品的第二项，其中所述乘积有条件地添加到中央处理单元中的第三项。中央处理单元包括进位保存加法器，其被配置为添加从第一项和第二项的乘积获得的多个部分乘积以获得第一部分结果和第二部分结果;多路复用器，被配置为输出从由第二项，第三项和第零组成的组，以及对准移位器，被配置为移位多路复用器的输出以使多路复用器的输出与第一部分结果和第二部分结果对齐以获得偏移项。将移位的项，第一部分结果和第二部分结果相加在一起以获得二进制操作的结果。

22. 发明授权

US07689642B1 Efficient accuracy check for Newton-Raphson divide and square-root operations 有权
标题翻译：牛顿 - 拉夫逊分割和平方根操作的有效精度检查
公开(公告)号：US07689642B1
公开(公告)日：2010-03-30
申请号：US11266838
申请日：2005-11-03
申请人： Leonard D. Rarick
发明人： Leonard D. Rarick
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5355
摘要： One embodiment of the present invention provides a system that efficiently performs an accuracy-check computation for Newton-Raphson divide and square-root operations. During operation, the system performs Newton-Raphson iterations followed by a multiply for the divide or square-root operation. This result is then rounded to produce a proposed result. Next, the system performs an accuracy-check computation to determine whether rounding the result to a desired precision produces the correct result. This accuracy-check computation involves performing a single pass through a multiply-add pipeline to perform a multiply-add operation. During this single pass, a Booth encoding of an operand in a multiply portion of the multiply-add pipeline is modified, if necessary, to cause an additional term for the accuracy-check computation to be added to the result of the multiply-add operation. In this way, the accuracy-check computation can be completed without requiring an additional pass through the multiply-add pipeline and without an additional partial-product row in the multiply-add pipeline.
摘要翻译：本发明的一个实施例提供了一种能够有效地执行牛顿 - 拉夫逊分割和平方根运算的精度检查计算的系统。在操作期间，系统执行牛顿 - 拉夫逊迭代，然后进行乘法除法或平方根操作。然后将该结果四舍五入以产生建议的结果。接下来，系统执行精度检查计算以确定将结果舍入到期望的精度是否产生正确的结果。此精确度检查计算涉及执行通过乘法加法管道的单次执行以执行乘法运算。在该单次通过期间，如果需要，修改乘法加法管道的乘法部分中的操作数的布斯编码，以便将精度检查计算的附加项添加到乘法运算的结果中。以这种方式，可以完成精度检查计算，而不需要额外的通过乘法加法管道，而在乘法加法管道中不需要额外的部分产品行。

23. 发明授权

US07684563B1 Apparatus and method for implementing a unified hash algorithm pipeline 有权
标题翻译：用于实现统一哈希算法流水线的装置和方法
公开(公告)号：US07684563B1
公开(公告)日：2010-03-23
申请号：US10968428
申请日：2004-10-19
申请人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
发明人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28
CPC分类号： H04L9/16 , G06F9/3895 , H04L9/0643 , H04L2209/125 , H04L2209/38
摘要： An apparatus and method for implementing a unified hash algorithm pipeline. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm is dynamically selectable from a plurality of hash algorithms, and where the hash logic comprises a plurality of pipeline stages each configured to compute a portion of the hash algorithm. The cryptographic unit may further include a word buffer configured to store the data block during computing by the hash logic.
摘要翻译：一种用于实现统一哈希算法流水线的装置和方法。在一个实施例中，密码单元可以包括哈希逻辑，其被配置为根据散列算法计算数据块的哈希值，其中散列算法可以从多个散列算法动态地选择，并且其中散列逻辑包括多个流水线级分别被配置为计算散列算法的一部分。加密单元还可以包括字缓冲器，其被配置为在由哈希逻辑计算期间存储数据块。

24. 发明授权

US07443981B1 Execution unit for performing the data encryption standard 有权
标题翻译：用于执行数据加密标准的执行单元
公开(公告)号：US07443981B1
公开(公告)日：2008-10-28
申请号：US10676554
申请日：2003-10-01
申请人： Leonard D. Rarick , Christopher H. Olson
发明人： Leonard D. Rarick , Christopher H. Olson
IPC分类号： H04K1/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译：适于执行数据加密标准的至少一部分的执行单元。执行单元包括左半输入; 一键输入和一个表输入。执行单元还包括被配置为接收表输入，执行表查找和输出数据的第一组晶体管。执行单元还包括具有两个输入和一个输出的第一个异或运算符。第一个独占或运算符被配置为接收左半输入和键输入。执行单元还包括具有两个输入和一个输出的第二个异或运算符。第二异或运算符被配置为接收由第一组晶体管输出的数据并且接收第一异或运算符的输出。执行单元还包括具有两个输入和一个输出的第三个异或运算符。第三个异或运算符被配置为接收第一组晶体管的左半输入和数据输出。

25. 发明授权

US07233965B2 Continuous random number generation method and apparatus 有权
标题翻译：连续随机数生成方法和装置
公开(公告)号：US07233965B2
公开(公告)日：2007-06-19
申请号：US10261308
申请日：2002-09-30
申请人： Leonard D. Rarick
发明人： Leonard D. Rarick
IPC分类号： G06F1/02
CPC分类号： G06F7/582 , G06F7/588
摘要： A method and apparatus for generating continuous random numbers. The method includes generating a value for a continuous random number using a continuous random number function with a plurality of iterations responsive to at least an input signal different from a request for the value and providing the value if the request for the value is received.
摘要翻译：一种用于产生连续随机数的方法和装置。该方法包括使用连续随机数函数生成连续随机数的值，该连续随机数函数响应至少一个不同于该值的请求的输入信号，并且如果接收到该值的请求，则提供该值，该迭代响应于多个迭代。

26. 发明授权

US07185043B2 Adder including generate and propagate bits corresponding to multiple columns 有权
标题翻译：加法器包括生成和传播与多列对应的位
公开(公告)号：US07185043B2
公开(公告)日：2007-02-27
申请号：US10601376
申请日：2003-06-23
申请人： Leonard D. Rarick
发明人： Leonard D. Rarick
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/508
摘要： An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the combiner units may provide a generate and propagate bit pair in response to receiving respective bits of the first and the second value which correspond to a plurality of the respective columns. The carry creation unit may create an ordered plurality of carry bits each corresponding to one or more of the generate and propagate bit pairs. Each of the summation units may generate a plurality of sum bits in response to receiving the respective bits of the first and the second value which correspond to the plurality of respective columns.
摘要翻译：一种用于添加包括多个比特的第一值和第二值的装置包括组合器单元，进位创建单元和求和单元。对应于第一和第二值的位位置的位形成相应的列。每个组合器单元可以响应于接收对应于多个相应列的第一和第二值的相应位而提供生成和传播位对。进位创建单元可以创建每个对应于生成和传播比特对中的一个或多个的有序多个进位。响应于接收对应于多个相应列的第一和第二值的各个比特，每个求和单元可以生成多个和比特。

27. 发明授权

US5504915A Modified Wallace-Tree adder for high-speed binary multiplier, structure and method 失效
标题翻译：用于高速二进制乘法器的修改华莱士树加法器，结构和方法
公开(公告)号：US5504915A
公开(公告)日：1996-04-02
申请号：US102683
申请日：1993-08-05
申请人： Leonard D. Rarick
发明人： Leonard D. Rarick
IPC分类号： G06F7/50 , G06F7/508 , G06F7/52
CPC分类号： G06F7/5318 , G06F7/509
摘要： A carry-save adder for use in a binary multiplier with a reduced number of full adder stages. The carry-save adder is for summing columns of binary data and is implemented with a plurality of one-bit and two-bit full adders. The one-bit and two-bit full adders are configured in a plurality of interconnected modified Wallace-Tree adders, each modified Wallace-Tree adder for summing binary data bits from one or more columns and generating a partial sum and a partial carry. Each modified Wallace-Tree adder has a plurality of stages comprising a combination of one-bit and two-bit full adders for reducing the number of the binary data bits, the last stage comprising a single one-bit full adder for generating the partial sum and partial carry results. A plurality of conductors interconnects the stages of each modified Wallace-Tree adder with stages in the same modified Wallace-Tree adder and with stages in other modified Wallace-Tree adders.
摘要翻译：一种进位保存加法器，用于具有减少数量的全加器级的二进制乘法器。进位保存加法器用于对二进制数据的列求和，并且用多个一位和两位全加器实现。一位和两位全加法器配置在多个互连的修改的Wallace-Tree加法器中，每个修改的Wallace-Tree加法器用于从一个或多个列求和二进制数据位，并产生部分和和部分进位。每个修改的华莱士树加法器具有多个级，包括用于减少二进制数据位的数目的一位和两位全加器的组合，最后一级包括用于产生部分和的单个一位全加器和部分携带结果。多个导体将每个修改的Wallace-Tree加法器的各级与相同的修改的Wallace-Tree加法器中的阶段和其他修改的Wallace-Tree加法器中的阶段相互连接。

28. 发明授权

US08990283B2 Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module 有权
标题翻译：在单个乘法模块中融合乘法加法和未加法乘法加法舍入
公开(公告)号：US08990283B2
公开(公告)日：2015-03-24
申请号：US13280180
申请日：2011-10-24
申请人： Murali K. Inaganti , Leonard D. Rarick
发明人： Murali K. Inaganti , Leonard D. Rarick
IPC分类号： G06F7/38 , G06F7/483 , G06F7/544
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014
摘要： A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.
摘要翻译：包括单个未融合融合的浮点乘法（FMA）模块的计算机处理器计算用于融合乘法加法运算和未加密乘法加法运算的浮点数的操作A * B + C的结果。在一个实施例中，利用额外的硬件来增加融合乘法加法实现，其中计算未加密的乘法加法结果，而不增加额外的流水线级。在一个实施例中，使用单个操作码来启动由融合未分配的浮点乘法（FMA）模块进行的计算，该操作码确定是否生成融合乘法加法结果或未合并的乘法加法结果。

29. 发明申请

US20120087492A1 EXECUTION UNIT FOR PERFORMING THE DATA ENCRYPTION STANDARD 有权
标题翻译：执行数据加密标准的执行单位
公开(公告)号：US20120087492A1
公开(公告)日：2012-04-12
申请号：US13291026
申请日：2011-11-07
申请人： Leonard D. Rarick , Christopher H. Olson
发明人： Leonard D. Rarick , Christopher H. Olson
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： Described is an execution unit for performing at least part of the Data Encryption Standard that includes a Left Half input; a Key input; and a Table input, as well as a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output that is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the data output by the first group of transistors.
摘要翻译：描述了用于执行包括左半输入的数据加密标准的至少一部分的执行单元; 一键输入和Table输入，以及被配置为接收Table输入的第一组晶体管，执行表查找和输出数据。执行单元还包括具有两个输入的第一异或运算符和被配置为接收左半输入和键输入的输出。执行单元还包括具有两个输入的第二异或运算符和被配置为接收由第一组晶体管输出的数据并且接收第一个异或运算符的输出的输出。执行单元还包括具有两个输入的第三异或运算符和被配置为接收左半输入和由第一组晶体管输出的数据的输出。

30. 发明申请

US20100329450A1 INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS 审中-公开
标题翻译：使用通用寄存器执行数据加密标准（DES）计算的说明
公开(公告)号：US20100329450A1
公开(公告)日：2010-12-30
申请号：US12494481
申请日：2009-06-30
申请人： Leonard D. Rarick , Christopher H. Olson , Gregory F. Grohoski
发明人： Leonard D. Rarick , Christopher H. Olson , Gregory F. Grohoski
IPC分类号： H04L9/06
CPC分类号： H04L9/0625 , H04L2209/122 , H04L2209/125
摘要： Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor.
摘要翻译：本发明的一些实施例提供一种处理器，其包括一组通用寄存器和至少一个执行单元。通用寄存器组中的每个通用寄存器至少为64位宽，执行单元支持一个或多个数据加密标准（DES）指令。具体地，执行单元可以支持用于执行DES置换操作和DES旋转操作的置换旋转指令。执行单元还可以支持执行DES循环操作的循环指令。由于DES指令使用通用寄存器而不是专用寄存器来执行DES特定操作，所以处理器的电路复杂度和面积减少。此外，在一些实施例中，由于DES指令需要至多两个操作数，所以指定操作数的位置所需的位数减少，从而使更多数量的指令由处理器支持。

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