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21. 发明授权

US07060619B2 Reduction of the shear stress in copper via's in organic interlayer dielectric material 有权
标题翻译：在有机层间介质材料中减少铜通道中的剪切应力
公开(公告)号：US07060619B2
公开(公告)日：2006-06-13
申请号：US10379346
申请日：2003-03-04
申请人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
发明人： Andy Cowley , Erdem Kaltalioglu , Mark Hoinkis , Michael Stetter
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76849 , H01L21/76877
摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
摘要翻译：形成包含逻辑电路（微处理器，Asics或其他）或随机存取存储器单元（DRAMS）的半导体主体上的互连层以显着减少相邻导体/通孔之间的短路数量的方式形成， 0.18微米或更小。这是通过蚀刻完成的，以在化学机械抛光工艺完成后在每一层上形成凹陷的铜顶表面。在凹陷的铜表面上施加的阻挡层的厚度被控制成与周围的绝缘体表面基本上共面。较厚的阻挡层消除了对覆盖层的需要。消除覆盖层导致整体电容耦合，应力和成本的降低。

22. 发明授权

US08378439B2 Methods of manufacturing semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的方法及其结构
公开(公告)号：US08378439B2
公开(公告)日：2013-02-19
申请号：US13310923
申请日：2011-12-05
申请人： Michael Beck , Erdem Kaltalioglu
发明人： Michael Beck , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76832
摘要： Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.
摘要翻译：公开了制造半导体器件的方法。优选实施例包括制造半导体器件的方法，该方法包括提供工件，在工件上设置蚀刻停止层，以及在蚀刻停止层上设置材料层。材料层包括过渡层。该方法包括以第一图案部分地图案化材料层，并以第二图案部分地图案化材料层。用第二图案部分地对材料层进行图案化还包括用第一图案同时完全图案化材料层。

23. 发明授权

US08093150B2 Methods of manufacturing semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的方法及其结构
公开(公告)号：US08093150B2
公开(公告)日：2012-01-10
申请号：US11523207
申请日：2006-09-19
申请人： Michael Beck , Erdem Kaltalioglu
发明人： Michael Beck , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76832
摘要： Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.
摘要翻译：公开了制造半导体器件的方法。优选实施例包括制造半导体器件的方法，该方法包括提供工件，在工件上设置蚀刻停止层，以及在蚀刻停止层上设置材料层。材料层包括过渡层。该方法包括以第一图案部分地图案化材料层，并以第二图案部分地图案化材料层。用第二图案部分地对材料层进行图案化还包括用第一图案同时完全图案化材料层。

24. 发明授权

US07795615B2 Capacitor integrated in a structure surrounding a die 有权
标题翻译：电容器集成在一个模具周围的结构中
公开(公告)号：US07795615B2
公开(公告)日：2010-09-14
申请号：US11268854
申请日：2005-11-08
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L23/58
CPC分类号： H01L23/5223 , H01L23/585 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.
摘要翻译：集成电路包括芯片，该芯片包括由周边区域包围的电路区域，该周边区域延伸到芯片的边缘。集成电路设置在电路区域内。外围区域内没有设置有源电路。屏障设置在外围区域内并且围绕电路区域。屏障包括集成在其中的电容器结构。

25. 发明申请

US20100022085A1 Method of Forming Support Structures for Semiconductor Devices 有权
标题翻译：形成半导体器件支撑结构的方法
公开(公告)号：US20100022085A1
公开(公告)日：2010-01-28
申请号：US12572905
申请日：2009-10-02
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L21/768 , G06F17/50
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/20754 , H01L2924/30105 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2224/05599
摘要： Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.
摘要翻译：公开了半导体器件的支撑结构及其制造方法。在一些实施例中，支撑结构包括在线接合区域下方形成为大致环形的多个支撑构件。多个支撑构件的大致环形形状内的中心区域可以用于路由功能导电线，用于与半导体器件的有源区电接触。可选地，在功能导电线之间形成虚拟支撑结构。支撑结构可以形成在半导体器件的一个或多个导电层和半导体材料层中。在其它实施例中，支撑构件不形成为环形，并且形成为不包括低介电常数（k）材料的绝缘层。

26. 发明申请

US20090194850A1 Crack Stops for Semiconductor Devices 有权
标题翻译：半导体器件的裂纹停止
公开(公告)号：US20090194850A1
公开(公告)日：2009-08-06
申请号：US12024758
申请日：2008-02-01
申请人： Erdem Kaltalioglu , Michael Beck
发明人： Erdem Kaltalioglu , Michael Beck
IPC分类号： H01L23/58 , H01L21/304
CPC分类号： H01L21/78 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.
摘要翻译：公开了用于半导体器件，半导体器件和制造半导体器件的方法的裂纹停止。在一个实施例中，用于半导体器件的阻挡结构包括多个基本上V形的区域。多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

27. 发明申请

US20080119039A1 Memory Card with Connecting Portions for Connection to an Adapter 有权
标题翻译：具有连接部分的存储卡，用于连接到适配器
公开(公告)号：US20080119039A1
公开(公告)日：2008-05-22
申请号：US12014539
申请日：2008-01-15
申请人： Klaus Herold , Erdem Kaltalioglu
发明人： Klaus Herold , Erdem Kaltalioglu
IPC分类号： H01L21/4763 , G06F9/45
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.
摘要翻译：公开了具有延伸端的导电线的半导体器件和将导线端部延伸可变距离的方法。互连结构的第一导电特征的端部延伸第一距离，并且互连结构的第二导电特征的端部延伸第二距离，第二距离不同于第一距离。位于靠近相邻导电特征的导电特征端部优选地不延伸。

28. 发明申请

US20070102787A1 Capacitor integrated in a structure surrounding a die 有权
标题翻译：电容器集成在一个模具周围的结构中
公开(公告)号：US20070102787A1
公开(公告)日：2007-05-10
申请号：US11268854
申请日：2005-11-08
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/585 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.
摘要翻译：集成电路包括芯片，该芯片包括由周边区域包围的电路区域，该周边区域延伸到芯片的边缘。集成电路设置在电路区域内。外围区域内没有设置有源电路。屏障设置在外围区域内并且围绕电路区域。屏障包括集成在其中的电容器结构。

29. 发明申请

US20070080464A1 Support structures for semiconductor devices 有权
标题翻译：半导体器件的支撑结构
公开(公告)号：US20070080464A1
公开(公告)日：2007-04-12
申请号：US11248554
申请日：2005-10-12
申请人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
发明人： Thomas Goebel , Erdem Kaltalioglu , Sun-Oo Kim
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/20754 , H01L2924/30105 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20755 , H01L2224/05599
摘要： Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.
摘要翻译：公开了半导体器件的支撑结构及其制造方法。在一些实施例中，支撑结构包括在线接合区域下方形成为大致环形的多个支撑构件。多个支撑构件的大致环形形状内的中心区域可以用于路由功能导电线，用于与半导体器件的有源区电接触。可选地，在功能导电线之间形成虚拟支撑结构。支撑结构可以形成在半导体器件的一个或多个导电层和半导体材料层中。在其它实施例中，支撑构件不形成为环形，并且形成为不包括低介电常数（k）材料的绝缘层。

30. 发明授权

US06638851B2 Dual hardmask single damascene integration scheme in an organic low k ILD 有权
标题翻译：有机低k ILD中的双重硬掩模单镶嵌整体方案
公开(公告)号：US06638851B2
公开(公告)日：2003-10-28
申请号：US09845305
申请日：2001-05-01
申请人： Andy Cowley , Erdem Kaltalioglu , Michael Stetter
发明人： Andy Cowley , Erdem Kaltalioglu , Michael Stetter
IPC分类号： H01L214763
CPC分类号： H01L21/76802
摘要： Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD) by: providing semiconductor substrate; depositing organic low k ILD layer on substrate; forming hardmask 1 on organic low k ILD layer and forming sacrificial hardmask 2 on hardmask 1; forming a patterned photoresist layer on sacrificial hardmask 2; etching selective to sacrificial hardmask 2 and stripping photoresist; etching of hardmask 1 in which the etch is selective to the organic low k ILD layer; depositing a liner or conformal barrier layer over the substrate, organic low k ILD layer, hardmask 1 and hardmask 2; forming a plated metal layer over the liner or conformal barrier layer; and removing metal layer and removing liner with simultaneous removal of sacrificial hardmask 2 so that facets in sacrificial hardmask 2 are removed during liner/sacrificial hardmask 2 removal.
摘要翻译：在有机低k层间电介质（ILD）中的单镶嵌工艺集成方案中使用双重无机硬掩模制造半导体的工艺：提供半导体衬底;在衬底上沉积有机低k ILD层;在有机低k ILD层上形成硬掩模1; 在硬掩模1上形成牺牲硬掩模2;在牺牲硬掩模2上形成图案化的光刻胶层;对牺牲硬掩模2进行选择性蚀刻和剥离光刻胶;蚀刻硬掩模1，其中蚀刻对有机低k ILD层是选择性的;沉积衬垫或在衬底上的共形阻挡层，有机低k ILD层，硬掩模1和硬掩模2;在衬里或保形阻挡层上形成电镀金属层; 并移除金属层，同时去除牺牲性硬掩模2，从而在衬垫/牺牲硬掩模2移除期间去除牺牲硬掩模2中的刻面。

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