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21. 发明申请

US20090096104A1 Semiconductor device having crack stop structure 有权
标题翻译：具有裂纹停止结构的半导体器件
公开(公告)号：US20090096104A1
公开(公告)日：2009-04-16
申请号：US12216097
申请日：2008-06-30
申请人： Kyoung-woo Lee , Hong-jae Shin
发明人： Kyoung-woo Lee , Hong-jae Shin
IPC分类号： H01L23/532
CPC分类号： H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.
摘要翻译：示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。层间绝缘层可以顺序堆叠在半导体衬底上。层间绝缘层可以包括第一双镶嵌图案和第一开口。可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

22. 发明授权

US06627540B2 Method for forming dual damascene structure in semiconductor device 失效
标题翻译：在半导体器件中形成双镶嵌结构的方法
公开(公告)号：US06627540B2
公开(公告)日：2003-09-30
申请号：US10233812
申请日：2002-09-03
申请人： Kyoung-woo Lee
发明人： Kyoung-woo Lee
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813
摘要： A method for forming a dual damascene structure in a semiconductor device, which is capable of preventing defects in node segregation between damascene interconnections and reducing parasitic capacitance, is provided. The method includes sequentially depositing an insulating structure layer including a via level insulating layer and a trench level insulating layer and a hard mask layer on a semiconductor substrate on which an underlying layer including a contact plug is formed, forming a via hole on the via level insulating layer using the hard mask layer, add forming a trench connected to the via hole in the insulating structure layer using the hard mask layer. A predetermined upper portion of the insulating structure layer and the hard mask layer are removed when the trench and the via hole are formed.
摘要翻译：提供了一种在半导体器件中形成双镶嵌结构的方法，其能够防止镶嵌互连之间的节点偏离和减小寄生电容的缺陷。该方法包括在其上形成有包括接触塞的下层的半导体衬底上依次沉积包括通孔层绝缘层和沟槽级绝缘层和硬掩模层的绝缘结构层，在通孔级上形成通孔使用硬掩模层的绝缘层，使用硬掩模层在绝缘结构层中形成连接到通孔的沟槽。当形成沟槽和通孔时，去除绝缘结构层和硬掩模层的预定上部。

23. 发明申请

US20090124093A1 Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
标题翻译：使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率
公开(公告)号：US20090124093A1
公开(公告)日：2009-05-14
申请号：US12353519
申请日：2009-01-14
申请人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
发明人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
IPC分类号： H01L21/469
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

24. 发明申请

US20080116521A1 CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same 审中-公开
标题翻译：使用具有高应力特性的绝缘层的CMOS集成电路，以改善NMOS和PMOS晶体管载体的迁移率和形成方法
公开(公告)号：US20080116521A1
公开(公告)日：2008-05-22
申请号：US11560564
申请日：2006-11-16
申请人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
发明人： Kyoung-woo Lee , Ja-hum Ku , Seung-man Choi
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
摘要翻译： CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

25. 发明申请

US20100060966A1 ACTUATOR USING PIEZOELECTRIC ELEMENT AND METHOD OF DRIVING THE SAME 审中-公开
标题翻译：使用压电元件的致动器及其驱动方法
公开(公告)号：US20100060966A1
公开(公告)日：2010-03-11
申请号：US12556793
申请日：2009-09-10
申请人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-Jong So , Hong-hee Kim
发明人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-Jong So , Hong-hee Kim
IPC分类号： G02B26/08 , G05B1/02 , G03H1/00
CPC分类号： H01L41/0825 , G02B26/0858 , H01L41/042
摘要： An actuator using a piezoelectric element and a method of driving the same. The actuator includes at least one piezoelectric cell moving by displacement according to an input voltage, at least one piezoelectric sensor sensing the displacement of the at least one piezoelectric cell, an error detector detecting an error in the at least one piezoelectric sensor, and a feedback signal generator generating a feedback signal corresponding to the error, thereby performing micromirror driving and sensing.
摘要翻译：使用压电元件的致动器及其驱动方法。致动器包括至少一个根据输入电压移动的压电单元，至少一个感测至少一个压电单元的位移的压电传感器，检测至少一个压电传感器中的误差的误差检测器和反馈信号发生器产生对应于该误差的反馈信号，由此执行微镜驱动和感测。

26. 发明申请

US20090194817A1 CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein 有权
标题翻译： CMOS集成电路器件已经在其中突出了NMOS和PMOS沟道区域
公开(公告)号：US20090194817A1
公开(公告)日：2009-08-06
申请号：US12420936
申请日：2009-04-09
申请人： Kyoung-woo Lee , Ja-hum Ku , Jae-eon Park
发明人： Kyoung-woo Lee , Ja-hum Ku , Jae-eon Park
IPC分类号： H01L27/092 , H01L23/48
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.
摘要翻译：形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

27. 发明授权

US07323407B2 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material 有权
标题翻译：使用扩散阻挡层对基材的微电子器件的双镶嵌互连的方法
公开(公告)号：US07323407B2
公开(公告)日：2008-01-29
申请号：US11195404
申请日：2005-08-02
申请人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
发明人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
IPC分类号： H01L21/311 , H01L23/52
CPC分类号： H01L21/76808 , H01L21/02134 , H01L21/3124 , H01L21/76826
摘要： Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0
摘要翻译：提供了适用于微电子器件的双镶嵌互连的方法和使用扩散阻挡层在加工期间防止基底材料的类似应用。所述方法包括以下步骤：用以通式（RSiO 3/2/2）x（HSiO 3/2/2）表示的氢倍半硅氧烷（HSQ））填料填充通孔 y，其中x和y满足关系x + y = 1和0

28. 发明授权

US07916371B2 Actuator for holographic information storing apparatus 失效
标题翻译：全息信息存储装置用致动器
公开(公告)号：US07916371B2
公开(公告)日：2011-03-29
申请号：US12391569
申请日：2009-02-24
申请人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-jong So , Hong-hee Kim
发明人： Young-min Cheong , Kyoung-woo Lee , Jae-hwan Kwon , Hyoung-jong So , Hong-hee Kim
IPC分类号： G02B26/08
CPC分类号： G02B26/0858
摘要： An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.
摘要翻译：一种用于驱动全息信息存储装置的反射镜的致动器，所述致动器包括：压电单元; 安装在压电单元上的支撑构件; 安装在所述支撑构件上的铰链构件; 以及安装在所述铰链构件上的支撑所述反射镜的柱。铰链构件包括平行于反射镜的旋转轴线设置的杆和从杆延伸的弯曲部分。

29. 发明授权

US07800134B2 CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein 有权
标题翻译： CMOS集成电路器件在其中具有应力的NMOS和PMOS沟道区
公开(公告)号：US07800134B2
公开(公告)日：2010-09-21
申请号：US12420936
申请日：2009-04-09
申请人： Kyoung-woo Lee , Ja-hum Ku , Jae-eon Park
发明人： Kyoung-woo Lee , Ja-hum Ku , Jae-eon Park
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor.
摘要翻译：形成CMOS集成电路器件的方法包括在半导体衬底中形成至少第一，第二和第三晶体管，然后用一个或多个赋予晶体管沟道区的净应力（拉伸或压缩）的电绝缘层覆盖晶体管。覆盖步骤可以包括用具有足够高的内应力特性的第一电绝缘层覆盖第一和第二晶体管，以在第一晶体管的沟道区域中施加净拉伸（或压缩）应力，并用第具有足够高的内应力特性的第二电绝缘层，以在第三晶体管的沟道区域中施加净压缩（或拉伸）应力。然后执行步骤以选择性地去除与第二晶体管的栅电极相对延伸的第二电绝缘层的第一部分。此外，可以执行步骤以选择性地去除与第一晶体管的栅极相对延伸的第一电绝缘层的第一部分和与第三晶体管的栅电极相对延伸的第二电绝缘层的第二部分。

30. 发明申请

US20090280637A1 Method of manufacturing semiconductor device including ultra low dielectric constant layer 审中-公开
标题翻译：包括超低介电常数层的半导体器件的制造方法
公开(公告)号：US20090280637A1
公开(公告)日：2009-11-12
申请号：US12453326
申请日：2009-05-07
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31695
摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层半导体器件。该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔，形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

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