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21. 发明授权

US06333528B1 Semiconductor device having a capacitor exhibiting improved moisture resistance 失效
标题翻译：具有显示改善的耐湿性的电容器的半导体装置
公开(公告)号：US06333528B1
公开(公告)日：2001-12-25
申请号：US09071795
申请日：1998-05-04
申请人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
发明人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11585 , H01L27/1159 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/75 , Y10S438/958
摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
摘要翻译：一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连在其他方面。通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

22. 发明授权

US6015987A Semiconductor device having capacitor exhibiting improved mositure resistance and manufacturing method thereof 失效
标题翻译：具有显示出改善的耐电阻性的电容器的半导体器件及其制造方法
公开(公告)号：US6015987A
公开(公告)日：2000-01-18
申请号：US71122
申请日：1998-05-04
申请人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
发明人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L27/108 , H01L29/00 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11585 , H01L27/1159 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/75 , Y10S438/958
摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
摘要翻译：一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连在其他方面。通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

23. 发明授权

US5624864A Semiconductor device having capacitor and manufacturing method thereof 失效
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US5624864A
公开(公告)日：1997-04-29
申请号：US284984
申请日：1994-08-04
申请人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
发明人： Koji Arita , Eiji Fujii , Yasuhiro Shimada , Yasuhiro Uemoto , Toru Nasu , Akihiro Matsuda , Yoshihisa Nagano , Atsuo Inoue , Taketoshi Matsuura , Tatsuo Otsuki
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11585 , H01L27/1159 , H01L28/40 , H01L28/55 , H01L28/60 , H01L28/75 , Y10S438/958
摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
摘要翻译：一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连在其他方面。通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

24. 发明授权

US06541375B1 DC sputtering process for making smooth electrodes and thin film ferroelectric capacitors having improved memory retention 失效
标题翻译：用于制造平滑电极的DC溅射工艺和具有改善的记忆保持力的薄膜铁电电容器
公开(公告)号：US06541375B1
公开(公告)日：2003-04-01
申请号：US09128249
申请日：1998-08-03
申请人： Shinichiro Hayashi , Koji Arita
发明人： Shinichiro Hayashi , Koji Arita
IPC分类号： H01L2144
CPC分类号： H01L28/75 , C23C14/08 , H01L21/2855 , H01L28/55 , H01L28/60
摘要： A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by DC reactive sputtering.
摘要翻译：铁电薄膜电容器具有平滑的电极，允许相对较强的极化，较少的疲劳和较少的压印，因为铁电电容器老化。光滑的电极表面由直流反应溅射制成。

25. 发明授权

US08759190B2 Current steering element and non-volatile memory element incorporating current steering element 有权
标题翻译：目前的导向元件和非易失性存储元件结合了当前的转向元件
公开(公告)号：US08759190B2
公开(公告)日：2014-06-24
申请号：US13823667
申请日：2011-09-16
申请人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
发明人： Ryoko Miyanaga , Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Koji Arita
IPC分类号： H01L21/20
CPC分类号： H01L45/16 , H01L21/768 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L45/00 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.
摘要翻译：一种形成为当前的操舵元件覆盖形成在层间绝缘层（102）中的通孔（104）的下开口（105）的电流控制元件（100），包括：形成在通孔的下开口的下侧，使得防蚀层覆盖下开口的整个部分; 形成在所述腐蚀抑制层下方并且包含不同于所述腐蚀抑制层的材料的材料的第二电极层（108）形成在所述第二电极层下方的电流转向层（110），使得所述电流导向层物理地与所述第二电极层接触; 以及第一电极层（112），形成在所述电流导向层下方，使得所述第一电极层物理地与所述电流转向层接触; 并且第一电极层，电流导向层和第二电极层构成MSM二极管和MIM二极管之一。

26. 发明申请

US20130224930A1 METHOD FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT 审中-公开
标题翻译：制造可变电阻元件的方法
公开(公告)号：US20130224930A1
公开(公告)日：2013-08-29
申请号：US13805198
申请日：2011-06-21
申请人： Koji Arita , Takumi Mikawa
发明人： Koji Arita , Takumi Mikawa
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2409 , H01L27/2418 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A variable resistance element manufacturing method includes: forming a conductive plug in an interlayer insulating film on a substrate; planarizing an upper surface of the insulating film such that an upper part of the conductive plug protrudes from an upper surface of the insulating film by removing (i) a depression in the insulating film formed around the conductive plug and (ii) a depression in the insulating film formed across a plurality of conductive plugs; forming, on the insulating film and the plug, a lower electrode layer electrically connected to the plug; planarizing an upper surface of the lower electrode layer to remove a protruding part on the upper surface of the lower electrode layer; forming, on the lower electrode layer, a variable resistance layer; forming an upper electrode layer on the variable resistance layer; and forming a lower electrode, the variable resistance layer, and an upper electrode layer.
摘要翻译：一种可变电阻元件制造方法，包括：在基板上的层间绝缘膜中形成导电插塞; 平面化绝缘膜的上表面，使得导电插塞的上部从绝缘膜的上表面突出，通过去除（i）形成在导电插塞周围的绝缘膜中的凹陷，以及（ii）形成在多个导电插塞上的绝缘膜; 在所述绝缘膜和所述插塞上形成电连接到所述插头的下电极层; 平面化下电极层的上表面以去除下电极层的上表面上的突出部分; 在下电极层上形成可变电阻层; 在所述可变电阻层上形成上电极层; 以及形成下电极，可变电阻层和上电极层。

27. 发明授权

US08394669B2 Resistance variable element and resistance variable memory device 有权
标题翻译：电阻可变元件和电阻变量存储器件
公开(公告)号：US08394669B2
公开(公告)日：2013-03-12
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L21/02 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

28. 发明授权

US08304908B2 Semiconductor device having a multilevel interconnect structure and method for fabricating the same 失效
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US08304908B2
公开(公告)日：2012-11-06
申请号：US12382624
申请日：2009-03-19
申请人： Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
发明人： Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/74
CPC分类号： H01L21/76853 , H01L21/288 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76861 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
摘要翻译：半导体器件中的多层互连结构包括形成在半导体晶片上的第一绝缘层，形成在第一绝缘层上的Cu互连层，形成在Cu互连层上的第二绝缘层和形成在界面处的金属氧化物层在Cu互连层和第二绝缘层之间。金属氧化物层通过在Cu互连层上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理而形成。

29. 发明申请

US20070190341A1 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070190341A1
公开(公告)日：2007-08-16
申请号：US11704950
申请日：2007-02-12
申请人： Akira Furuya , Koji Arita , Tetsuya Kurokawa , Kaori Noda
发明人： Akira Furuya , Koji Arita , Tetsuya Kurokawa , Kaori Noda
IPC分类号： C25D5/02 , B32B13/04
CPC分类号： C25D3/38 , C25D5/50 , C25D7/123 , C25D15/00 , H01L21/2885 , H01L21/76801 , H01L21/76829 , H01L21/76873 , H01L21/76877 , H01L21/76883
摘要： An improved SIV resistance and an improved EM resistance are achieved in the coupling structure containing copper films. A semiconductor device includes: a semiconductor substrate; a second insulating layer formed on or over the semiconductor substrate; a second barrier metal film, formed on the second insulating film, and being capable of preventing copper from diffusing into the second insulating film; and an electrically conducting film formed on the second barrier metal film so as to be in contact with the second barrier metal film, and containing copper and carbon, wherein a distribution of carbon concentration along a depositing direction in the second electrically conducting film includes a first peak and a second peak.
摘要翻译：在包含铜膜的耦合结构中实现了改进的SIV电阻和改进的EM电阻。半导体器件包括：半导体衬底; 形成在所述半导体衬底上或之上的第二绝缘层; 第二阻挡金属膜，形成在所述第二绝缘膜上，并且能够防止铜扩散到所述第二绝缘膜中; 以及形成在所述第二阻挡金属膜上以与所述第二阻挡金属膜接触并且含有铜和碳的导电膜，其中所述第二导电膜中沿着沉积方向的碳浓度的分布包括第一峰值和第二高峰。

30. 发明授权

US07132732B2 Semiconductor device having two distinct sioch layers 失效
标题翻译：半导体器件具有两个不同的透镜层
公开(公告)号：US07132732B2
公开(公告)日：2006-11-07
申请号：US10767786
申请日：2004-01-29
申请人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
发明人： Koichi Ohto , Tatsuya Usami , Noboru Morita , Sadayuki Ohnishi , Koji Arita , Ryohei Kitao , Yoichi Sasaki
IPC分类号： H01L23/58 , H01L23/48
CPC分类号： H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.
摘要翻译：半导体器件具有半导体衬底和设置在其上的多层布线装置。多层绞合装置包括其中形成有金属布线图案的至少一个绝缘层结构。绝缘层结构包括第一SiOCH层，形成在第一SiOCH层上的第二SiOCH层和形成在第二SiOCH层上的二氧化硅（SiO 2）层。第二SiOCH层的碳（C）密度低于第一SiOCH层的碳（C）密度，氢（H）密度低于第一SiOCH层的密度，氧（O）密度高于第一SiOCH层。

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