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21. 发明授权

US06535075B2 Tunable on-chip capacity 失效
标题翻译：可调芯片容量
公开(公告)号：US06535075B2
公开(公告)日：2003-03-18
申请号：US09737929
申请日：2000-12-15
申请人： Roland Frech , Erich Klink , Jochen Supper
发明人： Roland Frech , Erich Klink , Jochen Supper
IPC分类号： H03H701
CPC分类号： H01L27/0805
摘要： The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors. By tuning the total capacity (CSD) of the decoupling capacitors a resonance condition of the resonance loop (40) is met under which a minimum of switching power noise and a minimum switching power consumption is achieved.
摘要翻译：本发明涉及一种用于半导体芯片（10）的可调片上容量电路，该半导体芯片（10）安装在基板（30）上并且包括多个电源去耦电容器（20-23），该电源去耦电容器可通过接通而被选择性地激活或去激活或关闭供电系统。片上检测电路（32）确定片上电源网络的电路特定的负载/卸载频率，响应于检测电路的信号的片上控制装置（28,33）增加或减少片上容量（CSD）通过选择性地激活或去激活电源去耦电容器（20-23）。片外路径阻抗（LMC，RMC），片外容量（CM）和片上容量（CC），包括多个电源去耦电容器（20-23）和寄生片上容量（ CP）形成谐振回路（40），其可通过改变片上电源去耦电容器的总容量（CSD）来调节。通过调谐去耦电容器的总容量（CSD），满足谐振回路（40）的谐振条件，在该谐振回路（40）的谐振条件下达到最小开关功率噪声和最小开关功耗。

22. 发明授权

US06442041B2 MCM—MLC technology 失效
标题翻译： MCM-MLC技术
公开(公告)号：US06442041B2
公开(公告)日：2002-08-27
申请号：US09740280
申请日：2000-12-19
申请人： Simone Rehm , Bernd Garden , Erich Klink , Gisbert Thomke , William F. Shutler
发明人： Simone Rehm , Bernd Garden , Erich Klink , Gisbert Thomke , William F. Shutler
IPC分类号： H05K702
CPC分类号： H05K1/0224 , H01L23/5383 , H01L23/5384 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0253 , H05K1/0289 , H05K1/0298 , H05K2201/09681 , H01L2924/00
摘要： Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.
摘要翻译：公开了一种多层电子封装结构，特别适用于多芯片模块。通过由相应的网状导体形成信号导体的重叠，实现了改进的屏蔽效果，并且减少了信号导线之间的耦合。通过增加通孔冲压间距，使得在相邻通路之间形成多个布线通道，可改善布线性，并且可以减少信号分布层的数量。因此，新结构显示出比现有技术结构更好的电性能，同时成本降低约35％。

23. 发明授权

US5157635A Input signal redriver for semiconductor modules 失效
标题翻译：用于半导体模块的输入信号转接器
公开(公告)号：US5157635A
公开(公告)日：1992-10-20
申请号：US728831
申请日：1991-07-09
申请人： Wayne F. Ellis , Erich Klink , Knut Najmann
发明人： Wayne F. Ellis , Erich Klink , Knut Najmann
IPC分类号： G11C7/22 , G11C8/18
CPC分类号： G11C8/18 , G11C7/22
摘要： A semiconductor packaging subassembly is described in which a plurality of modules or chips, repsonsive to a plurality of common input signals, are provided with input signal redriver circuits. Each redriver circuit is responsive to an input and provides an output signal to each the of chips in the subassembly. The preferred embodiment is directed to a multi-module memory arrangement in which input signals including CAS, RAS, W and address signals are received and redriven.
摘要翻译：描述了一种半导体封装子组件，其中对多个公共输入信号重现的多个模块或芯片设置有输入信号转接电路。每个转接电路响应于输入，并向子组件中的每个芯片提供输出信号。优选实施例涉及一种多模块存储装置，其中包括CAS，RAS，W和地址信号的输入信号被接收并重新驱动。

24. 发明授权

US09134364B2 Determining the current return path integrity in an electric device connected or connectable to a further device 有权
标题翻译：确定连接或可连接到另一设备的电气设备中的当前返回路径完整性
公开(公告)号：US09134364B2
公开(公告)日：2015-09-15
申请号：US13565159
申请日：2012-08-02
申请人： Roland Frech , Erich Klink , Jürgen Saalmüller
发明人： Roland Frech , Erich Klink , Jürgen Saalmüller
IPC分类号： G01R27/28 , G01R31/08 , G01R31/28 , G01R27/16 , G01R31/02 , G01R31/3185 , H04B3/487
CPC分类号： G01R27/28 , G01R27/16 , G01R31/025 , G01R31/046 , G01R31/2839 , G01R31/31855 , H04B3/487
摘要： A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.
摘要翻译：一种用于确定具有多个信号线和电源线的电气设备中的当前返回路径完整性的方法。提供了在另一个定义的信号线上由输入信号产生的限定的信号线上具有近端串扰信号的至少一个参考信号图案的库，施加到电气设备的选定信号线的预定信号，检测到电气设备的至少一个其它信号线上的端串扰信号，将所述近端串扰信号与来自库的相应参考信号模式进行比较，并且如果近端串扰信号与相应的参考信号之间存在偏差信号图案，显示电气设备中存在任何缺陷的信息。

25. 发明授权

US08248082B2 Method for determining the current return path integrity in an electric device connected or connectable to a further device 失效
标题翻译：用于确定连接或可连接到另一设备的电气设备中的当前返回路径完整性的方法
公开(公告)号：US08248082B2
公开(公告)日：2012-08-21
申请号：US12523119
申请日：2007-11-20
申请人： Roland Frech , Erich Klink , Jurgen Saalmuller
发明人： Roland Frech , Erich Klink , Jurgen Saalmuller
IPC分类号： G01R27/28 , G01R31/08
CPC分类号： G01R27/28 , G01R27/16 , G01R31/025 , G01R31/046 , G01R31/2839 , G01R31/31855 , H04B3/487
摘要： A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.
摘要翻译：一种用于确定具有多个信号线和电源线的电气设备中的当前返回路径完整性的方法。提供了在另一个定义的信号线上由输入信号产生的限定的信号线上具有近端串扰信号的至少一个参考信号图案的库，施加到电气设备的选定信号线的预定信号，检测到电气设备的至少一个其它信号线上的端串扰信号，将所述近端串扰信号与来自库的相应参考信号模式进行比较，并且如果近端串扰信号与相应的参考信号之间存在偏差信号图案，显示电气设备中存在任何缺陷的信息。

26. 发明申请

US20100109679A1 METHOD FOR DETERMINING THE CURRENT RETURN PATH INTEGRITY IN AN ELECTRIC DEVICE CONNECTED OR CONNECTABLE TO A FURTHER DEVICE 失效
标题翻译：用于确定连接或连接到另一设备的电气设备中的电流返回路径完整性的方法
公开(公告)号：US20100109679A1
公开(公告)日：2010-05-06
申请号：US12523119
申请日：2007-11-20
申请人： Roland Frech , Erich Klink , Jurgen Saalmuller
发明人： Roland Frech , Erich Klink , Jurgen Saalmuller
IPC分类号： G06F19/00 , G01R27/28
CPC分类号： G01R27/28 , G01R27/16 , G01R31/025 , G01R31/046 , G01R31/2839 , G01R31/31855 , H04B3/487
摘要： A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.
摘要翻译：一种用于确定具有多个信号线和电源线的电气设备中的当前返回路径完整性的方法。提供了在另一个定义的信号线上由输入信号产生的限定的信号线上具有近端串扰信号的至少一个参考信号图案的库，施加到电气设备的选定信号线的预定信号，检测到电气设备的至少一个其它信号线上的端串扰信号，将所述近端串扰信号与来自库的相应参考信号模式进行比较，并且如果近端串扰信号与相应的参考信号之间存在偏差信号图案，显示电气设备中存在任何缺陷的信息。

27. 发明申请

US20070109726A1 Printed circuit board and chip module 有权
标题翻译：印刷电路板和芯片模块
公开(公告)号：US20070109726A1
公开(公告)日：2007-05-17
申请号：US11281688
申请日：2005-11-17
申请人： Wiren Becker , Bruce Chamberlin , Roland Frech , Andreas Huber , George Katopis , Erich Klink , Andreas Rebmann , Thomas-Michael Winkel
发明人： Wiren Becker , Bruce Chamberlin , Roland Frech , Andreas Huber , George Katopis , Erich Klink , Andreas Rebmann , Thomas-Michael Winkel
IPC分类号： H02B1/00
CPC分类号： H05K1/0262 , H05K1/0298 , H05K1/141 , H05K2201/093 , H05K2201/09327 , H05K2201/09663
摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.
摘要翻译：本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

28. 发明授权

US06218631B1 Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk 失效
标题翻译：用于减少VLSI电路中串扰的结构及其使用填充通道的方法，以尽量减少串扰
公开(公告)号：US06218631B1
公开(公告)日：2001-04-17
申请号：US09115365
申请日：1998-07-14
申请人： Asmus Hetzel , Erich Klink , Juergen Koehl , Dieter Wendel , Parsotam Trikam Patel
发明人： Asmus Hetzel , Erich Klink , Juergen Koehl , Dieter Wendel , Parsotam Trikam Patel
IPC分类号： H01R1204
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure for reducing cross-talk in VLSI circuits is disclosed. By filling voltage and ground metal lines in free or unused channels of VLSI chips and connecting them efficiently to the regular power image of the chip, the line to line coupling through vertical layers is reduced almost to zero and in-layer line to line coupling is also drastically reduced.
摘要翻译：公开了一种用于减少VLSI电路串扰的结构。通过在VLSI芯片的自由或未使用通道中填充电压和接地金属线，并将它们有效地连接到芯片的常规功率图像，通过垂直层的线对线耦合几乎减少到零，并且层间线对线耦合也大幅减少。

29. 发明授权

US6043724A Two-stage power noise filter with on and off chip capacitors 失效
标题翻译：两级功率噪声滤波器，带有片上电容和片外电容
公开(公告)号：US6043724A
公开(公告)日：2000-03-28
申请号：US15231
申请日：1998-01-29
申请人： Roland Frech , Erich Klink , William F. Shutler , Ulrich Weiss , Thomas-Michael Winkel
发明人： Roland Frech , Erich Klink , William F. Shutler , Ulrich Weiss , Thomas-Michael Winkel
IPC分类号： H01G4/40 , H01L21/822 , H01L25/00 , H01L27/04 , H03L7/099 , H04B15/00 , H03H7/06
CPC分类号： H04B15/00 , H03L7/099 , H01L2224/16225 , H01L2924/15312
摘要： Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.
摘要翻译：描述了用于电力噪声敏感电路的中高频模块（片外）/片上功率噪声滤波器的新颖实现。为了实现这一点，使用二阶低通方法。第一级电容器位于模块（片外）上，第二级电容器在片上实现。

30. 发明授权

US5914533A Multilayer module with thinfilm redistribution area 失效
标题翻译：具有薄膜再分配区域的多层模块
公开(公告)号：US5914533A
公开(公告)日：1999-06-22
申请号：US765989
申请日：1997-01-10
申请人： Roland Frech , Hubert Harrer , Erich Klink , William F. Shutler
发明人： Roland Frech , Hubert Harrer , Erich Klink , William F. Shutler
IPC分类号： H01L23/538 , H01L23/522 , H01L23/34
CPC分类号： H01L23/5385 , H01L2224/16225 , H01L2924/09701 , H01L2924/15184 , H01L2924/15312 , H01L2924/3011
摘要： The invention relates to a multilayer module 20 for packaging of at least one electronic component, such as the integrated circuit chips 21, 22. The module 20 comprises a thickfilm structure and a thinfilm structure. The thinfilm structure provides an interface between the electronic components and the thickfilm structure. The thinfilm structure comprises a first powerplane and a redistribution wiring structure. The topmost layer of conductors of the thickfilm structure is a second powerplane so that an electrical structure approaching a triplate structure is realized.
摘要翻译： PCT No.PCT / EP95 / 02153 Sec。 371日期1997年1月10日 102（e）日期1997年1月10日PCT Filed June 6，1995 PCT Pub。公开号WO96 / 39716 PCT 日期：1996年12月12日本发明涉及一种用于封装至少一个电子部件（例如集成电路芯片21,22）的多层模块20.模块20包括厚膜结构和薄膜结构。薄膜结构提供了电子部件和厚膜结构之间的界面。薄膜结构包括第一电源线和再分配布线结构。厚膜结构的最顶层的导体是第二功率平面，从而实现接近三板结构的电结构。

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