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21. 发明申请

US20080230845A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20080230845A1
公开(公告)日：2008-09-25
申请号：US11859043
申请日：2007-09-21
申请人： Kensuke Okonogi , Kiyonori Ohyu
发明人： Kensuke Okonogi , Kiyonori Ohyu
IPC分类号： H01L29/78 , H01L23/52 , H01L21/4763
CPC分类号： H01L29/7834 , H01L21/26506 , H01L21/28525 , H01L21/76843 , H01L21/76859 , H01L23/53271 , H01L29/66628 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.
摘要翻译：半导体器件可以包括但不限于单晶硅扩散层，多晶硅导体和扩散阻挡层。扩散阻挡层将多晶硅导体与单晶硅扩散层分离。扩散阻挡层防止在单晶硅扩散层和多晶硅导体之间的硅间隙和硅空位中的至少一个的扩散。

22. 发明授权

US07186632B2 Method of fabricating a semiconductor device having a decreased concentration of phosphorus impurities in polysilicon 失效
标题翻译：制造在多晶硅中磷杂质浓度降低的半导体器件的方法
公开(公告)号：US07186632B2
公开(公告)日：2007-03-06
申请号：US10395724
申请日：2003-03-24
申请人： Kazuo Ogawa , Kiyonori Ohyu , Kensuke Okonogi , Toshihiro Imamura , Keiichi Watanabe , Hiroyuki Ohta
发明人： Kazuo Ogawa , Kiyonori Ohyu , Kensuke Okonogi , Toshihiro Imamura , Keiichi Watanabe , Hiroyuki Ohta
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28247 , H01L21/28061
摘要： In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2×1020(1/cm3) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.
摘要翻译：在具有层叠栅电极的半导体器件的制造方法中，在栅极氧化膜上形成磷掺杂多晶硅。在多晶硅上形成高熔点金属或高熔点金属和硅的化合物。将磷掺杂到多晶硅中，使得多晶硅和栅极氧化物膜之间的界面处的多晶硅中的磷的浓度为2×10 20（1 / cm 3）或更少。然后，在含有水蒸气的湿氢气氛中进行热氧化。

23. 发明授权

US5374582A Laminated substrate for semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置用层叠基板及其制造方法
公开(公告)号：US5374582A
公开(公告)日：1994-12-20
申请号：US233940
申请日：1994-04-28
申请人： Kensuke Okonogi , Hiroaki Kikuchi
发明人： Kensuke Okonogi , Hiroaki Kikuchi
IPC分类号： H01L21/18 , H01L21/761 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76251 , H01L21/187 , H01L21/761 , Y10S148/012
摘要： A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed on a buried layer of P type formed in the region of N type in which the power device is formed and surrounded by a isolating region of P type reaching the buried layer from the surface of the laminated substrate.
摘要翻译：一种用于制造半导体器件的层压衬底的方法，所述半导体器件具有形成在与具有P-N结的功率器件隔离的区域中的高电压功率器件和低电压元件。低电压元件的区域形成在形成有功率器件的N型区域中形成的P型掩埋层，并且由层叠衬底的表面到达掩埋层的P型隔离区包围。

24. 发明授权

US06448157B1 Fabrication process for a semiconductor device 失效
标题翻译：半导体器件的制造工艺
公开(公告)号：US06448157B1
公开(公告)日：2002-09-10
申请号：US09494491
申请日：2000-01-31
申请人： Kensuke Okonogi , Takuo Ohashi
发明人： Kensuke Okonogi , Takuo Ohashi
IPC分类号： H01L21322
CPC分类号： H01L29/66613 , H01L21/02238 , H01L21/02255 , H01L21/02312 , H01L21/31662 , H01L21/3221 , H01L21/3225 , H01L21/76202 , H01L21/7621 , H01L29/66621 , Y10S438/928
摘要： A surface of a substrate is oxidized at a temperature equal to or higher than 1050° C., or at a oxidation speed equal to or higher than 7.5 nm/min to form an oxide film with a thickness equal to or more than 1500 nm. when the oxide film is removed, a density of pits existent at the surface of a substrate is equal to or less than that prior to the oxidation treatment and a depth of a pit existent there is equal to or less than 50 nm. An element isolation withstand voltage can be prevented from lowering and a fabrication yield of a miniaturized, highly integrated semiconductor device can be improved.
摘要翻译：基板的表面在等于或高于1050℃的温度或等于或高于7.5nm / min的氧化速度下被氧化，形成厚度等于或大于1500nm的氧化膜。当除去氧化物膜时，在基板表面存在的凹坑的密度等于或小于氧化处理之前的凹坑的密度，并且存在凹坑的深度等于或小于50nm。可以防止元件隔离耐压降低，并且可以提高小型化，高度集成的半导体器件的制造成品率

25. 发明授权

US5970366A Method of removing metallic contaminants from simox substrate 失效
标题翻译：从simox底物去除金属污染物的方法
公开(公告)号：US5970366A
公开(公告)日：1999-10-19
申请号：US895034
申请日：1997-07-16
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/265 , H01L21/322 , H01L27/12
CPC分类号： H01L21/26533 , H01L21/3221
摘要： In a method of forming a silicon substrate, a gettering film is formed on a bottom surface of a silicon substrate. An oxygen ion implantation into a top surface of the silicon substrate is carried out at a substrate temperature in the range of 400.degree. C.-700.degree. C. The gettering film is removed from the silicon substrate. The silicon substrate is subjected to a heat treatment at a temperature of not less than 1300.degree. C. for causing a reaction of oxygen and silicon to form a silicon oxide film in the silicon substrate after the gettering film is removed.
摘要翻译：在形成硅衬底的方法中，在硅衬底的底表面上形成吸气膜。在400℃〜700℃的范围内的基板温度下进行氧离子注入到硅衬底的顶表面中。从硅衬底去除吸气膜。在不小于1300℃的温度下对硅衬底进行热处理，以在除去膜之后在硅衬底中引起氧和硅的反应形成氧化硅膜。

26. 发明授权

US5420064A Method of manufacturing a dielectric isolation substrate 失效
标题翻译：电介质隔离衬底的制造方法
公开(公告)号：US5420064A
公开(公告)日：1995-05-30
申请号：US310076
申请日：1994-09-22
申请人： Kensuke Okonogi , Tsukasa Ohoka
发明人： Kensuke Okonogi , Tsukasa Ohoka
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76297 , Y10S148/012 , Y10S148/135
摘要： According to this invention, there is provided a method of manufacturing a semiconductor device, including the steps of anisotropically etching a surface of an n-type monocrystalline silicon substrate having the (100) plane to form a V-shaped isolation groove having a depth d.sub.1, performing ion implantation and performing annealing and diffusion to a surface of the V-shaped isolation groove to form an n.sup.+ -type buried layer, depositing a silicon dioxide film having a thickness d.sub.2 on a surface of the n.sup.+ -type buried layer, forming a polycrystalline silicon film on a surface of the silicon dioxide film, abrading and polishing the polycrystalline silicon film to have a thickness d.sub.3, adhering a monocrystalline silicon support substrate having a thickness d.sub.4 to a polished surface of the polycrystalline silicon film at room temperature in the atmospheric air, abrading and polishing a lower surface of the n-type monocrystalline silicon substrate having the V-shaped isolation groove to expose the silicon dioxide film at a bottom portion of the V-shaped isolation groove on the lower surface and to form an island-like monocrystalline silicon film, wherein the thicknesses d.sub.1, d.sub.2, d.sub.3, and d.sub.4 are set to be 50 to 60 .mu.m, 1 to 3 .mu.m, 0 to 30 .mu.m, and 350 to 450 .mu.m, respectively.
摘要翻译：根据本发明，提供一种制造半导体器件的方法，包括以下步骤：对具有（100）面的n型单晶硅衬底的表面进行各向异性蚀刻，以形成具有深度d1的V形隔离槽，进行离子注入并对V形隔离槽的表面进行退火和扩散，形成n +型掩埋层，在n +型掩埋层的表面上沉积厚度为d2的二氧化硅膜，形成在二氧化硅膜的表面上形成多晶硅膜，研磨和研磨多晶硅膜以具有厚度d3，在大气中室温下将具有厚度d4的单晶硅支撑基板粘附到多晶硅膜的抛光表面空气，研磨和研磨具有V形隔离槽的n型单晶硅衬底的下表面以暴露s 在下表面的V形隔离槽的底部形成二氧化钛膜，形成岛状单晶硅膜，其中厚度d1，d2，d3和d4设定为50〜60μm， 1〜3亩，0〜30亩，350〜450亩。

27. 发明授权

US06323109B1 Laminated SOI substrate and producing method thereof 失效
标题翻译：叠层SOI衬底及其制造方法
公开(公告)号：US06323109B1
公开(公告)日：2001-11-27
申请号：US09187846
申请日：1998-11-06
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L2130
CPC分类号： H01L21/3226 , H01L21/76254 , Y10S438/977
摘要： An insulation film is formed on a first single crystal silicon substrate, e.g., a hydrogen anneal substrate, an intrinsic gettering substrate and an epitaxial substrate. Hydrogen implantation is carried out from a surface of this insulation film, thereby forming a hydrogen implantation region in the first single crystal silicon substrate. Then, by carrying out a thermal treatment at 400 to 500° C., voids are formed in the hydrogen implantation region, and the first single crystal silicon substrate is cleaved therefrom. Next, the surface of the insulation film and a surface of a second single crystal silicon substrate are laminated and then, they are subjected to a thermal treatment at 1,000° C. or higher. With this method, the adverse influence, on a device, of defects in the substrate can be reduced and a yield can be enhanced.
摘要翻译：绝缘膜形成在第一单晶硅衬底上，例如氢退火衬底，固有吸气衬底和外延衬底。从该绝缘膜的表面进行氢注入，从而在第一单晶硅衬底中形成氢注入区。然后，通过在400〜500℃进行热处理，在氢注入区域形成空隙，从而使第一单晶硅衬底从其中裂开。接下来，将绝缘膜的表面和第二单晶硅衬底的表面层叠，然后在1000℃以上进行热处理。通过这种方法，可以降低衬底上的缺陷对器件的不利影响，并且可以提高产率。

28. 发明授权

US6057036A Semiconductor substrate having a serious effect of gettering heavy metal and method of manufacturing the same 失效
标题翻译：具有重吸收重金属的重要作用的半导体衬底及其制造方法
公开(公告)号：US6057036A
公开(公告)日：2000-05-02
申请号：US160352
申请日：1993-11-29
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/322 , H01L21/84 , H01L27/12 , B32B17/06
CPC分类号： H01L21/3226 , H01L21/3221 , Y10T428/12528
摘要： A silicon dioxide layer overlies a monocrystal silicon substrate and has a first upper surface. A first monocrystal silicon layer overlies the first upper surface and has phosphorus atoms diffused. A second monocrystal silicon layer overlies the first monocrystal silicon layer. The first monocrystal silicon layer may have phosphorus or silicon atoms each of which has a positive electric charge instead of the phosphorus atoms diffused. A lattice mismatching layer may overlie the first upper surface instead of the first monocrystal silicon layer. The lattice mismatching layer has parts in each of which misfit dislocation is caused. The first and the second monocrystal silicon layers may overlie the monocrystal silicon substrate and layer, respectively. In this event, a silicon glass layer is interposed between the first and the second monocrystal silicon layers. The second monocrystal silicon layer has phosphorus atoms diffused.
摘要翻译：二氧化硅层覆盖在单晶硅衬底上并具有第一上表面。第一单晶硅层覆盖第一上表面并且具有扩散的磷原子。第二单晶硅层覆盖在第一单晶硅层上。第一单晶硅层可以具有磷或硅原子，其各自具有正电荷而不是扩散的磷原子。晶格失配层可以覆盖第一上表面而不是第一单晶硅层。晶格失配层具有引起错位错位的部分。第一和第二单晶硅层可以分别覆盖在单晶硅衬底和层上。在这种情况下，硅玻璃层插入在第一和第二单晶硅层之间。第二单晶硅层具有扩散的磷原子。

29. 发明授权

US5798294A Semiconductor substrate having a serious effect of gettering heavy metal and method of manufacturing the same 失效
公开(公告)号：US5798294A
公开(公告)日：1998-08-25
申请号：US446056
申请日：1995-05-19
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/02 , H01L21/322 , H01L21/84 , H01L27/12
CPC分类号： H01L21/3226 , H01L21/3221 , Y10T428/12528
摘要： A silicon dioxide layer overlies a monocrystal silicon substrate and has a first upper surface. A first monocrystal silicon layer overlies the first upper surface and has phosphorus atoms diffused. A second monocrystal silicon layer overlies the first monocrystal silicon layer. The first monocrystal silicon layer may have phosphorus or silicon atoms each of which has a positive electric charge instead of the phosphorus atoms diffused. A lattice mismatching layer may overlie the first upper surface instead of the first monocrystal silicon layer. The lattice mismatching layer has parts in each of which misfit dislocation is caused. The first and the second monocrystal silicon layers may overlie the monocrystal silicon substrate and layer, respectively. In this event, a silicon glass layer is interposed between the first and the second monocrystal silicon layers. The second monocrystal silicon layer has phosphorus atoms diffused.

30. 发明授权

US5726089A Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5726089A
公开(公告)日：1998-03-10
申请号：US562790
申请日：1995-11-27
申请人： Kensuke Okonogi
发明人： Kensuke Okonogi
IPC分类号： H01L21/762 , H01L21/18 , H01L21/20 , H01L21/76 , H01L21/302
CPC分类号： H01L21/185 , H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76283 , H01L21/76286
摘要： A method for fabricating a semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.
摘要翻译：公开了一种用于制造具有能够减少其功率元件形成区域中的晶体缺陷的键合晶片结构的半导体器件的方法。在第一n-硅衬底的控制电路元件形成区域中形成凹部，然后填充硅并进行研磨和抛光以提供镜面。在第二n +硅衬底的表面上形成n外延层，然后将外延层的表面耦合到第一衬底的氧化硅膜和第二电路区的表面，并进行热处理以与其结合。

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