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21. 发明申请

US20090109741A1 DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR 失效
标题翻译：根据部分绝缘硅绝缘体的状态确定数据保留装置中数据的历史状态
公开(公告)号：US20090109741A1
公开(公告)日：2009-04-30
申请号：US11924955
申请日：2007-10-26
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C11/34
CPC分类号： G11C29/50 , G11C11/41 , G11C29/56 , G11C2029/0403 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1203
摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.
摘要翻译：公开了集成电路和设计结构。集成电路可以包括：数据保持装置; 电耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）装置; 以及耦合到所述PD SOI器件的测量装置，用于测量所述PD SOI器件的表示其体电压的状态，所述测量装置通信地耦合到计算装置，所述计算装置基于所述计算装置确定所述数据保持装置中的数据的历史状态测量PD SOI器件的状态。

22. 发明授权

US07732949B2 System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly 有权
标题翻译：用于在间歇电力环境中预测电力事件的方法的系统，并相应地调度集成电路的计算操作
公开(公告)号：US07732949B2
公开(公告)日：2010-06-08
申请号：US11550573
申请日：2006-10-18
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G05F3/06 , G06F1/00
CPC分类号： C09K11/77 , G06F1/3203
摘要： A system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译：一种在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的系统和方法。功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路。一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

23. 发明申请

US20090125744A1 Structure for a System and Method of Predicting Power Events in an Intermittent Power Environment and Dispatching Computational Operations of an Integrated Circuit Accordingly 有权
标题翻译：一种系统的结构和预测间歇电力环境中的电力事件的方法和集成电路的调度运算
公开(公告)号：US20090125744A1
公开(公告)日：2009-05-14
申请号：US11938899
申请日：2007-11-13
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译：一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路。一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

24. 发明申请

US20080285338A1 DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR 失效
标题翻译：根据部分绝缘硅绝缘体的状态确定数据保留装置中数据的历史状态
公开(公告)号：US20080285338A1
公开(公告)日：2008-11-20
申请号：US12180776
申请日：2008-07-28
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C11/34
CPC分类号： G11C11/417
摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.
摘要翻译：公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

25. 发明申请

US20080151672A1 DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE 有权
标题翻译：基于充电储存装置的可能性确定使用数据保留装置的相对数量
公开(公告)号：US20080151672A1
公开(公告)日：2008-06-26
申请号：US12045744
申请日：2008-03-11
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C7/00
CPC分类号： G06F12/121 , G06F12/122
摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
摘要翻译：公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

26. 发明授权

US07397718B2 Determining relative amount of usage of data retaining device based on potential of charge storing device 有权
标题翻译：基于电荷存储装置的潜力确定数据保存装置的相对使用量
公开(公告)号：US07397718B2
公开(公告)日：2008-07-08
申请号：US11279639
申请日：2006-04-13
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C7/00
CPC分类号： G06F12/121 , G06F12/122
摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
摘要翻译：公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

27. 发明授权

US07353486B2 Data processing in digital systems 有权
标题翻译：数字系统中的数据处理
公开(公告)号：US07353486B2
公开(公告)日：2008-04-01
申请号：US11272884
申请日：2005-11-14
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.
摘要翻译：包括用于缓解瓶颈的FPGA（现场可编程门阵列）的结构以及用于操作该结构的方法。 FPGA包括多个FPGA元件，每个FPGA元件包括CLB（可配置逻辑块），指令队列和数据缓冲器。可以通过第一本地IO（输入/输出）电路在FPGA中形成一个功能块（彼此分开）并移动到第二个本地IO电路。在每个功能块内，映射的逻辑位置函数计算从存储在映射位置寄存器中的功能块的当前位置以及存储在映射的目的地寄存器中的目的地的步长的方向，距离和时间，以及时间允许移动，并将步进的方向和距离存储在映射运动寄存器中。然后，功能块根据存储在映射运动寄存器中的方向和距离移动。

28. 发明授权

US06658634B1 Logic power optimization algorithm 失效
标题翻译：逻辑功率优化算法
公开(公告)号：US06658634B1
公开(公告)日：2003-12-02
申请号：US09073999
申请日：1998-05-07
申请人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.
摘要翻译：公开了一种用于消除在逻辑网络中不必要的逻辑切换的系统和方法。该方法和系统可以直接并入逻辑综合软件中，或者可以手动实现。提供了用于识别关键网络，然后在关键网络处插入网络锁存器的机制，其中每个网络锁存器由也控制相关输出锁存器的使能信号控制。每个网络锁存器包括一个电路，该电路可以在命令上保持给定逻辑节点上的最后一个逻辑电平。

29. 发明授权

US06996795B2 Data processing in digital systems 失效
标题翻译：数字系统中的数据处理
公开(公告)号：US06996795B2
公开(公告)日：2006-02-07
申请号：US10729750
申请日：2003-12-04
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.
摘要翻译：包括用于缓解瓶颈的FPGA（现场可编程门阵列）的结构以及用于操作该结构的方法。 FPGA包括多个FPGA元件，每个FPGA元件包括CLB（可配置逻辑块），指令队列和数据缓冲器。可以通过第一本地IO（输入/输出）电路在FPGA中形成一个功能块（彼此分开）并移动到第二个本地IO电路。在每个功能块内，映射的逻辑位置函数计算从存储在映射位置寄存器中的功能块的当前位置以及存储在映射的目的地寄存器中的目的地的步长的方向，距离和时间，以及时间允许移动，并将步进的方向和距离存储在映射运动寄存器中。然后，功能块根据存储在映射运动寄存器中的方向和距离移动。

30. 发明授权

US08575964B2 Inactivity triggered self clocking logic family 有权
标题翻译：不活动触发自我计时逻辑家族
公开(公告)号：US08575964B2
公开(公告)日：2013-11-05
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

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