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21. 发明授权

US07977932B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07977932B2
公开(公告)日：2011-07-12
申请号：US12206907
申请日：2008-09-09
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G05F3/16
CPC分类号： G05F1/465
摘要： The present invention provides a regulator circuit that can fast-respond to a variation in load current and supply a sufficient drive current so as to be capable of generating a stable internal source voltage. The regulator circuit includes a preamplifier circuit that detects and amplifies a different between a reference voltage and an internal source voltage, a clamp circuit that limits the amplitude of an output of the preamplifier circuit, a main amplifier circuit that amplifies the amplitude-limited output of the preamplifier circuit, and a driver circuit that outputs the internal source voltage according to the output of the main amplifier. Even though the internal source voltage varies abruptly, the regulator circuit does not oscillate owing to the effect of the clamp circuit.
摘要翻译：本发明提供了一种调节器电路，其能够快速响应负载电流的变化并提供足够的驱动电流，以便能够产生稳定的内部源电压。调节器电路包括前置放大器电路，其检测和放大参考电压和内部源极电压之间的不同，限制前置放大器电路的输出的幅度的钳位电路，放大限幅输出的主放大器电路前置放大器电路和根据主放大器的输出输出内部源电压的驱动电路。即使内部源电压突然变化，调节器电路也不会由于钳位电路的影响而振荡。

22. 发明授权

US07910975B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07910975B2
公开(公告)日：2011-03-22
申请号：US10593275
申请日：2005-06-03
申请人： Fukashi Morishita , Kazutami Arimoto
发明人： Fukashi Morishita , Kazutami Arimoto
IPC分类号： H01L29/788 , H01L27/01 , H01L27/12
CPC分类号： G11C11/405 , G11C2211/4016 , H01L27/108 , H01L27/10802
摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.
摘要翻译：本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。栅电极连接到栅极线，杂质扩散区连接到源极线。存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。杂质扩散区域连接到位线。

23. 发明授权

US07906990B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07906990B2
公开(公告)日：2011-03-15
申请号：US12677745
申请日：2008-09-19
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： H01L25/00 , H03K19/00 , H03K19/20
CPC分类号： H01L27/1203 , H01L27/088 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L29/7841 , H01L29/78615
摘要： The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.
摘要翻译：本发明提供一种半导体集成电路器件，其中SOI晶体管的特性被有效地用于实现更高的速度，更高的集成度，并且还降低了电压和功耗。根据本发明的半导体集成电路器件具有这样的结构，其中多个外部电源线和体电压控制线在一个方向上交替布置，以便在整个芯片上延伸，从而将电源和体电压提供给逻辑电路，模拟电路和存储器电路。体电压控制型逻辑门完全应用在逻辑电路中，而体电压控制型逻辑门部分地应用于存储器电路中。

24. 发明申请

US20080252388A1 Oscillator and charge pump circuit using the same 失效
公开(公告)号：US20080252388A1
公开(公告)日：2008-10-16
申请号：US12155876
申请日：2008-06-11
申请人： Masanobu Kishida , Fukashi Morishita
发明人： Masanobu Kishida , Fukashi Morishita
IPC分类号： H03B1/00
CPC分类号： H03K3/0315 , H03K17/063
摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

25. 发明授权

US07095272B2 Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage 失效
公开(公告)号：US07095272B2
公开(公告)日：2006-08-22
申请号：US11210845
申请日：2005-08-25
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

26. 发明申请

US20060024918A1 Semiconductor memory device and manufacturing method of the same 失效
公开(公告)号：US20060024918A1
公开(公告)日：2006-02-02
申请号：US11236668
申请日：2005-09-28
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/46
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

27. 发明授权

US06914300B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06914300B2
公开(公告)日：2005-07-05
申请号：US10653198
申请日：2003-09-03
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/84 , H01L23/52 , H01L27/01 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/786 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/84
摘要： In a potential interconnection layer, when viewed from a plane, a plurality of power supply potential regions and ground potential regions are alternately provided, with an interlayer insulation layer lying therebetween. A contact plug penetrating a second insulation layer is provided to electrically connect a source/drain (S/D) region on one side of a selected field effect transistor with a selected power supply potential region. Similarly, a contact plug penetrating the second insulation layer is provided to electrically connect a source/drain (S/D) region on the other side of another selected field effect transistor with a selected ground potential region. By employing this structure, a semiconductor device having a plurality of semiconductor circuits in which a power supply potential and a ground potential can be stabilized regardless of the cross-sectional structure of the semiconductor device is provided.
摘要翻译：在潜在的互连层中，当从平面观察时，交替地设置多个电源电位区域和接地电位区域，层间绝缘层位于其间。提供穿透第二绝缘层的接触插塞以将选定的场效应晶体管的一侧上的源极/漏极（S / D）区域与选定的电源电位区域电连接。类似地，穿过第二绝缘层的接触插塞被提供以将另一个选择的场效应晶体管的另一侧上的源极/漏极（S / D）区域与选择的接地电位区域电连接。通过采用这种结构，提供了具有能够稳定电源电位和接地电位的多个半导体电路的半导体器件，而与半导体器件的横截面结构无关。

28. 发明授权

US06781431B2 Clock generating circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US06781431B2
公开(公告)日：2004-08-24
申请号：US10349033
申请日：2003-01-23
申请人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
发明人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
IPC分类号： G06F104
CPC分类号： H03K3/0315 , H02M3/07 , H03K3/013 , H03K3/70
摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.
摘要翻译：用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

29. 发明授权

US06501326B2 Semiconductor integrated circuit 失效
公开(公告)号：US06501326B2
公开(公告)日：2002-12-31
申请号：US09849392
申请日：2001-05-07
申请人： Nobuyuki Fujii , Fukashi Morishita , Akira Yamazaki , Yasuhiko Taito , Mako Okamoto
发明人： Nobuyuki Fujii , Fukashi Morishita , Akira Yamazaki , Yasuhiko Taito , Mako Okamoto
IPC分类号： G05F110
CPC分类号： H02M3/073 , G05F1/465
摘要： A capacitor (C12) is connected between a node (L) in a double boost part and the ground, and the amplitude of a repetitive pulse from the node (L) is made less than twice that of the power-supply voltage through utilization of charge and discharge of the capacitor (C12).

30. 发明授权

US06483357B2 Semiconductor device reduced in through current 失效
标题翻译：半导体器件通过电流减小
公开(公告)号：US06483357B2
公开(公告)日：2002-11-19
申请号：US09811578
申请日：2001-03-20
申请人： Hiroshi Kato , Fukashi Morishita
发明人： Hiroshi Kato , Fukashi Morishita
IPC分类号： H03L700
CPC分类号： G05F1/465
摘要： A sense signal IVOFF is generated by a power supply level sense circuit with an external power supply potential Ext.Vcc1 as the operating power supply potential to sense the level of an external power supply potential Ext.Vcc2. By suppressing generation of an internal power supply potential or fixing the internal node by the sense signal IVOFF, the through current at the time of power on can be reduced.
摘要翻译：感测信号IVOFF由电源电平检测电路产生，外部电源电位Ext.Vcc1作为工作电源电位，用于感测外部电源电位Ext.Vcc2的电平。通过抑制内部电源电位的产生或通过感测信号IVOFF固定内部节点，可以减少上电时的通过电流。

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