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21. 发明授权

US06275399B1 Method and apparatus for driving a semiconductor element with variable resistance circuitry 失效
标题翻译：用可变电阻电路驱动半导体元件的方法和装置
公开(公告)号：US06275399B1
公开(公告)日：2001-08-14
申请号：US09654892
申请日：2000-09-05
申请人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
发明人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
IPC分类号： H02M768
CPC分类号： H03K17/0822 , H03K17/165
摘要： In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.
摘要翻译：在用于导通或中断主电流的功率半导体元件的驱动装置中，根据控制电压改变第一电阻的第一电阻变量，以及根据第一和第二电压之间的电压来改变第二电阻的第二电阻变量端子，并且控制电源的电压或第一和第二端子之间的电压中的任一个被第一电阻和第二电阻分压，并且分压被施加到控制栅极端子执行或中断主电流的时间。

22. 发明授权

US06204717B1 Semiconductor circuit and semiconductor device for use in equipment such as a power converting apparatus 失效
标题翻译：用于诸如电力转换装置的设备的半导体电路和半导体器件
公开(公告)号：US06204717B1
公开(公告)日：2001-03-20
申请号：US08651875
申请日：1996-05-21
申请人： Masahiro Nagasu , Hideo Kobayashi , Hideki Miyazaki , Shin Kimura , Junichi Sakano , Mutsuhiro Mori
发明人： Masahiro Nagasu , Hideo Kobayashi , Hideki Miyazaki , Shin Kimura , Junichi Sakano , Mutsuhiro Mori
IPC分类号： H03K508
CPC分类号： H01L29/866 , H01L29/0692 , H01L29/0834 , H01L29/7393 , H01L29/7395 , H03K17/08148 , H03K17/0828
摘要： A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby prevent the occurrence of the electromagnetic noise and the excessively large voltage.
摘要翻译：半导体电路或半导体器件具有电流 - 电压特性，在半导体电路或半导体器件的阻挡状态下，电流缓慢地流过等于或大于第一电压值但等于或等于或小于第二电压，而电流突然流过大于第二电压值的电压值。由于电流 - 电压特性，电路中提供的电感中积累的能量被半导体电路或半导体的差分电阻消耗，从而防止电磁噪声的发生和过大的电压。

23. 发明授权

US5767555A Compound semiconductor device controlled by MIS gate, driving method therefor and electric power conversion device using the compound semiconductor device and the driving method 失效
标题翻译：由MIS门控制的复合半导体器件，其驱动方法和使用该化合物半导体器件的驱动方法和电力转换器件
公开(公告)号：US5767555A
公开(公告)日：1998-06-16
申请号：US612457
申请日：1996-03-07
申请人： Junichi Sakano , Hideo Kobayashi , Masahiro Nagasu , Mutsuhiro Mori
发明人： Junichi Sakano , Hideo Kobayashi , Masahiro Nagasu , Mutsuhiro Mori
IPC分类号： H01L29/10 , H01L29/745 , H01L29/749 , H01L29/76
CPC分类号： H01L29/7455 , H01L29/102 , H01L29/749
摘要： A compound semiconductor device including a MISFET and a thyristor connected in series wherein either the withstanding voltage between the MISFET p base layer and the thyristor p base layer is set lower than the withstanding voltage of the MISFET, the MISFET is turned off under a condition that the MISFET p base layer and the thyristor p base layer are connected via a p channel or the lateral resistance of the thyristor p base layer is reduced, thereby the safe operating region of the compound semiconductor device is extended.
摘要翻译：一种复合半导体器件，包括MISFET和串联连接的晶闸管，其中MISFET p基极层和晶闸管p基极层之间的耐受电压设定为低于MISFET的耐受电压，MISFET在以下条件下关断： MISFET p基极层和晶闸管p基极层通过ap沟道连接，或者晶闸管p基极层的横向电阻降低，从而延长了化合物半导体器件的安全工作区域。

24. 发明授权

US08299836B2 Level shift circuit and power conversion unit 有权
标题翻译：电平移位电路和电源转换单元
公开(公告)号：US08299836B2
公开(公告)日：2012-10-30
申请号：US13029341
申请日：2011-02-17
申请人： Naoki Sakurai , Junichi Sakano , Seigoh Yukutake
发明人： Naoki Sakurai , Junichi Sakano , Seigoh Yukutake
IPC分类号： H03L5/00
CPC分类号： H03K19/0175
摘要： In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.
摘要翻译：在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

25. 发明申请

US20120018776A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20120018776A1
公开(公告)日：2012-01-26
申请号：US13187552
申请日：2011-07-21
申请人： Takuo Nagase , Junichi Sakano
发明人： Takuo Nagase , Junichi Sakano
IPC分类号： H01L29/78 , H01L29/861 , H01L29/739
CPC分类号： H01L29/7824 , H01L21/76264 , H01L29/0615 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/7391 , H01L29/7394
摘要： A first annular isolation trench is formed in a periphery of an element region, and a second annular isolation trench is formed around the first annular isolation trench with a predetermined distance provided from the first annular isolation trench, and a semiconductor layer between the first annular isolation trench and the second annular isolation trench is separated into a plurality of portions by a plurality of linear isolation trenches formed in the semiconductor layer between the first annular isolation trench and the second annular isolation trench, and the semiconductor layer (source-side isolation region) which opposes a p-type channel layer end portion and is located between the first annular isolation trench and the second annular isolation trench is separated from other semiconductor layers (drain-side isolation regions) by the linear isolation trenches.
摘要翻译：第一环形隔离沟槽形成在元件区域的周边中，并且第二环形隔离沟槽围绕第一环形隔离沟槽以从第一环形隔离沟槽提供的预定距离形成，并且在第一环形隔离沟槽之间的半导体层并且所述第二环形隔离沟槽通过形成在所述第一环形隔离沟槽和所述第二环形隔离沟槽之间的所述半导体层中的多个线性隔离沟槽分离成多个部分，并且所述半导体层（源极侧隔离区域）与第一环形隔离沟槽和第二环形隔离沟槽之间的p型沟道层端部相对的区域通过线性隔离沟槽与其它半导体层（漏极侧隔离区域）分离。

26. 发明申请

US20110227626A1 LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT 有权
标题翻译：电平转换电路和电源转换单元
公开(公告)号：US20110227626A1
公开(公告)日：2011-09-22
申请号：US13029341
申请日：2011-02-17
申请人： Naoki SAKURAI , Junichi Sakano , Seigoh Yukutake
发明人： Naoki SAKURAI , Junichi Sakano , Seigoh Yukutake
IPC分类号： H03L5/00
CPC分类号： H03K19/0175
摘要： In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.
摘要翻译：在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

27. 发明申请

US20060273400A1 High voltage analog switch ICS and ultrasound imaging systems using same 审中-公开
标题翻译：高压模拟开关ICS和超声波成像系统使用相同
公开(公告)号：US20060273400A1
公开(公告)日：2006-12-07
申请号：US11350930
申请日：2006-02-10
申请人： Taiga Arai , Junichi Sakano
发明人： Taiga Arai , Junichi Sakano
IPC分类号： H01L29/94
CPC分类号： H01L27/0738 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0852 , H01L29/1045 , H01L29/1083 , H01L29/7816 , H01L29/7835
摘要： A MOSFET including a JFET resistor resultant between a drain region and a channel region caused by depletion of current carriers. Since most of the drain-source voltage is imposed on the JFET resistor, the voltage imposed on a channel region is reduced to prevent concentration of an electric field therein. The JFET resistor adjusts the saturation current of the MOSFET and hence the width of the gate electrode can be sufficiently secured. This also prevents concentration of an electric field onto the channel region. In the MOSFET, the saturation current is reduced while avoiding creation of hot carriers. It is therefore possible to provide an MOSFET suitable for an analog switch.
摘要翻译：一种MOSFET，其包括由漏极区域和由电流载流子的耗尽引起的沟道区域之间产生的JFET电阻器。由于大部分漏极 - 源极电压被施加在JFET电阻上，所以施加在沟道区上的电压降低，以防止其中的电场集中。 JFET电阻调节MOSFET的饱和电流，因此可以充分确保栅电极的宽度。这也防止了电场在通道区域上的集中。在MOSFET中，饱和电流降低，同时避免了热载流子的产生。因此，可以提供适合于模拟开关的MOSFET。

28. 发明授权

US06392908B1 Method and apparatus for driving a semiconductor element 有权
公开(公告)号：US06392908B1
公开(公告)日：2002-05-21
申请号：US09884930
申请日：2001-06-21
申请人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
发明人： Hideki Miyazaki , Katsunori Suzuki , Koji Tateno , Junichi Sakano , Masahiro Iwamura , Mutsuhiro Mori
IPC分类号： H02M7521
摘要： In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.

29. 发明授权

US08698194B2 Semiconductor integrated circuit with high withstand voltage element forming trench isolation on substrate 失效
标题翻译：具有高耐压元件的半导体集成电路在衬底上形成沟槽隔离
公开(公告)号：US08698194B2
公开(公告)日：2014-04-15
申请号：US13187552
申请日：2011-07-21
申请人： Takuo Nagase , Junichi Sakano
发明人： Takuo Nagase , Junichi Sakano
IPC分类号： H01L29/66 , H01L21/70 , H01L27/12
CPC分类号： H01L29/7824 , H01L21/76264 , H01L29/0615 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/4238 , H01L29/7391 , H01L29/7394
摘要： A first annular isolation trench is formed in a periphery of an element region, and a second annular isolation trench is formed around the first annular isolation trench with a predetermined distance provided from the first annular isolation trench, and a semiconductor layer between the first annular isolation trench and the second annular isolation trench is separated into a plurality of portions by a plurality of linear isolation trenches formed in the semiconductor layer between the first annular isolation trench and the second annular isolation trench, and the semiconductor layer (source-side isolation region) which opposes a p-type channel layer end portion and is located between the first annular isolation trench and the second annular isolation trench is separated from other semiconductor layers (drain-side isolation regions) by the linear isolation trenches.
摘要翻译：第一环形隔离沟槽形成在元件区域的周边中，并且第二环形隔离沟槽围绕第一环形隔离沟槽以从第一环形隔离沟槽提供的预定距离形成，并且在第一环形隔离沟槽之间的半导体层并且所述第二环形隔离沟槽通过形成在所述第一环形隔离沟槽和所述第二环形隔离沟槽之间的所述半导体层中的多个线性隔离沟槽分离成多个部分，并且所述半导体层（源极侧隔离区域）与第一环形隔离沟槽和第二环形隔离沟槽之间的p型沟道层端部相对的区域通过线性隔离沟槽与其它半导体层（漏极侧隔离区域）分离。

30. 发明申请

US20130236189A1 COMMUNICATIONS SYSTEM 有权
标题翻译：通信系统
公开(公告)号：US20130236189A1
公开(公告)日：2013-09-12
申请号：US13885182
申请日：2010-12-27
申请人： Keisuke Yamamoto , Hiroshi Shinoda , Takahide Terada , Junichi Sakano , Kohei Onda
发明人： Keisuke Yamamoto , Hiroshi Shinoda , Takahide Terada , Junichi Sakano , Kohei Onda
IPC分类号： H04B10/80
CPC分类号： H04B10/808 , H01P1/30
摘要： In order to provide a communication system which performs a communication while maintaining high voltage insulation, a control circuit which is operated at a low voltage, and a controlled circuit which is operated at a high voltage are connected through a propagation layer having a waveguide structure, thereby performing a communication. In particular, a displacement current (surge current) flows between a high voltage circuit and a low voltage circuit due to a potential fluctuation which occurs in the high voltage circuit A surge current protection circuit is provided, and applying of an input which is out of rating to the communication module and the low voltage circuit due to such a surge current is prevented.
摘要翻译：为了提供一种在保持高电压绝缘的同时进行通信的通信系统，以低电压操作的控制电路和以高电压操作的受控电路通过具有波导结构的传播层连接，从而进行通信。特别地，由于在高电压电路A中发生的电位波动，高压电路和低压电路之间的位移电流（浪涌电流）流动，提供了浪涌电流保护电路，防止了由于这种浪涌电流引起的通信模块和低压电路的额定值。

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