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21. 发明授权

US08087020B2 Method and system for performing real-time operation 有权
标题翻译：执行实时操作的方法和系统
公开(公告)号：US08087020B2
公开(公告)日：2011-12-27
申请号：US12247509
申请日：2008-10-08
申请人： Tatsunori Kanai , Seiji Maeda , Hirokuni Yano , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Hirokuni Yano , Kenichiro Yoshii
IPC分类号： G06F9/46 , G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F9/4887 , G06F1/3203 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.
摘要翻译：信息处理系统以特定的时间间隔周期性地执行实时操作。该系统包括用于执行调度操作的单元，该调度操作将实时操作分配给处理器，以由处理器以特定时间间隔周期性地执行实时操作，用于计算实际的执行时间的比率的单元基于具体的时间间隔和关于处理器以第一操作速度进行实时操作所需的时间的成本信息，处理器以第一操作速度执行的时间操作，以及用于执行操作速度控制操作以在低于第一操作速度的第二操作速度下操作处理器，基于所计算的比率来确定第二操作速度。

22. 发明授权

US07739457B2 Local memory management system with plural processors 失效
标题翻译：具有多个处理器的本地存储器管理系统
公开(公告)号：US07739457B2
公开(公告)日：2010-06-15
申请号：US11751728
申请日：2007-05-22
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
IPC分类号： G06F12/10
CPC分类号： G06F9/544 , G06F9/5016
摘要： An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
摘要翻译：信息处理系统包括具有第一本地存储器的第一处理器，具有第二本地存储器的第二处理器和具有第三本地存储器的第三处理器。该系统还包括一个单元，其将第一和第三本地存储器之一映射到要由第一处理器执行的第一线程的有效地址空间的一部分。第二和第三本地存储器中映射的一个是第二和第三处理器中对应的一个处理器的本地存储器，其执行与第一线程交互的第二线程。该系统还包括将本地存储器改变为将第一线程的有效地址空间的一部分映射到第二和第三本地存储器之一的单元。

23. 发明授权

US07730249B2 Device control apparatus that calls an operating system to control a device 失效
标题翻译：调用操作系统来控制设备的设备控制设备
公开(公告)号：US07730249B2
公开(公告)日：2010-06-01
申请号：US11896848
申请日：2007-09-06
申请人： Kenichiro Yoshii , Tatsunori Kanai , Hiroshi Yao
发明人： Kenichiro Yoshii , Tatsunori Kanai , Hiroshi Yao
IPC分类号： G06F13/24
CPC分类号： G06F21/575 , G06F9/45537 , G06F9/4812
摘要： In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.
摘要翻译：在设备控制装置中，根据软件操作的处理器，OS存储单元存储在处理器上操作的操作系统，存储单元存储在处理器上操作的特许软件。当处理器从设备接收到中断时，特权软件会调用其中一个操作系统，并且操作系统控制该设备。此外，检测单元检测到处理器的中断，判断单元从检测到中断开始，在第一预定时间内判断操作系统是否从存储单元中调用了特权软件，并且当判断单元复位时，复位单元复位处理器单元判断操作系统9em没有从存储单元中调用特权软件。

24. 发明申请

US20080282249A1 METHOD AND SYSTEM FOR PERFORMING REAL-TIME OPERATION 有权
标题翻译：执行实时操作的方法和系统
公开(公告)号：US20080282249A1
公开(公告)日：2008-11-13
申请号：US12172285
申请日：2008-07-14
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/5066
摘要： An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
摘要翻译：信息处理系统执行包括多个任务的组合的实时操作。该系统包括多个处理器，存储结构描述信息的单元和描述与任务相对应的过程的多个程序，表示程序之间的输入/输出中的关系的结构性描述信息，并且包括关于执行所需时间的成本信息每个程序，基于结构描述信息确定用于执行程序的多个线程中的每一个的执行开始时间和执行项的单元，以及执行将线程分配至少的调度操作的单元根据确定的结果，处理器中的一个。

25. 发明申请

US20080244229A1 Information processing apparatus 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20080244229A1
公开(公告)日：2008-10-02
申请号：US11898880
申请日：2007-09-17
申请人： Hiroshi Yao , Kenichiro Yoshii , Tatsunori Kanai
发明人： Hiroshi Yao , Kenichiro Yoshii , Tatsunori Kanai
IPC分类号： G06F9/30
CPC分类号： G06F9/45533 , G06F9/30189 , G06F9/3836 , G06F9/3859
摘要： In an information processing apparatus, a fetch to a storage address of a first storage unit which stores a first instruction executed at first within a plurality of instructions that is included in a software and executed when a processor starts the software via the channel is detected. It is detected that the processor executed a specific instruction within the plurality of instructions via the channel. It is determined whether a predetermined time has passed since the detection of the fetch to the storage address until the detection of the execution of the specific instruction. When it is determined that the predetermined time has not passed, it is determined whether an interrupt to the processor is prohibited based on a result of the processor executing the specific instruction, and an access is released to the process according to a result of determination.
摘要翻译：在信息处理装置中，检索存储第一指令的存储地址的第一存储单元的存储地址，该第一指令首先在包括在软件中的多个指令中并且当处理器经由该通道启动软件时执行。检测到处理器经由信道在多个指令内执行特定指令。从检测到存储地址的检测到确定特定指令的执行的检测之前，确定是否已经过去了预定的时间。当确定尚未经过预定时间时，根据处理器执行特定指令的结果确定是否禁止对处理器的中断，并根据确定结果将访问释放到处理中。

26. 发明授权

US07359956B2 Data transfer scheme using caching and differential compression techniques for reducing network load 失效
标题翻译：数据传输方案采用缓存和差分压缩技术来减少网络负载
公开(公告)号：US07359956B2
公开(公告)日：2008-04-15
申请号：US10094462
申请日：2002-03-11
申请人： Tatsunori Kanai , Toshibumi Seki , Kenichiro Yoshii , Hideaki Sato , Takayuki Miyazawa , Haruhiko Toyama , Yasuhiro Kimura , Hideki Yoshida
发明人： Tatsunori Kanai , Toshibumi Seki , Kenichiro Yoshii , Hideaki Sato , Takayuki Miyazawa , Haruhiko Toyama , Yasuhiro Kimura , Hideki Yoshida
IPC分类号： G06F15/16 , H03M7/34
CPC分类号： H04L29/06 , H04L67/2852 , H04L67/2876 , H04L69/04
摘要： In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Even when the name corresponding to the data is not registered so that it is impossible to transfer the corresponding name instead of transferring the data, it is possible to reduce the amount of transfer data among the data transfer devices by transferring the compressed data in which this data is expressed in a compressed form by utilizing the name corresponding to the registered reference data.
摘要翻译：在使用缓存技术和/或压缩技术的数据传输方案中，能够减少在数据传输设备之间连接的网络的网络负载，数据和它们的名称之间的对应关系被登记在数据传输设备上，并且相应的名称是而是传送数据，而不是传送数据，对于其对应被登记的那些数据，使得可以减少数据传送装置之间的传送数据量。即使当与数据相对应的名称没有被登记使得不可能传送相应的名称而不是传送数据时，也可以通过传送数据传送装置中的这种数据的压缩数据来减少传送数据的数量通过利用与注册的参考数据对应的名称，以压缩形式表示数据。

27. 发明申请

US20070220230A1 LOCAL MEMORY MANAGEMENT SYSTEM WITH PLURAL PROCESSORS 失效
标题翻译：具有多种处理器的本地存储管理系统
公开(公告)号：US20070220230A1
公开(公告)日：2007-09-20
申请号：US11751728
申请日：2007-05-22
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii
IPC分类号： G06F9/34
CPC分类号： G06F9/544 , G06F9/5016
摘要： An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
摘要翻译：信息处理系统包括具有第一本地存储器的第一处理器，具有第二本地存储器的第二处理器和具有第三本地存储器的第三处理器。该系统还包括一个单元，其将第一和第三本地存储器之一映射到要由第一处理器执行的第一线程的有效地址空间的一部分。第二和第三本地存储器中映射的一个是第二和第三处理器中对应的一个处理器的本地存储器，其执行与第一线程交互的第二线程。该系统还包括将本地存储器改变为将第一线程的有效地址空间的一部分映射到第二和第三本地存储器之一的单元。

28. 发明授权

US08219767B2 Information processing apparatus and data recovering method 有权
标题翻译：信息处理装置和数据恢复方法
公开(公告)号：US08219767B2
公开(公告)日：2012-07-10
申请号：US12199111
申请日：2008-08-27
申请人： Kenichiro Yoshii , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
发明人： Kenichiro Yoshii , Hiroshi Yao , Tomohide Jokan , Tatsunori Kanai
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F11/1441 , G06F1/30
摘要： A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
摘要翻译：信息处理装置包括：在上一次修改时，指示将存储的主存储单元的存储内容写入主存储单元的存储内容中的顺序号，用于识别是否回写到主存储器单元从存储在备用存储器单元中的备份数据需要存储在序列号存储单元中的序列号。信息处理装置选择包括表示完全进行写入的完整性验证数据的备份数据。信息处理装置提取所选择的备份数据中包含的原始数据和写入目的地地址，并将原始数据和从备份数据提取的写入地址的原始数据写入主存储器单元的存储区域，由写入目标地址指示。

29. 发明授权

US07685599B2 Method and system for performing real-time operation 失效
标题翻译：执行实时操作的方法和系统
公开(公告)号：US07685599B2
公开(公告)日：2010-03-23
申请号：US10935188
申请日：2004-09-08
申请人： Tatsunori Kanai , Seiji Maeda , Hirokuni Yano , Kenichiro Yoshii
发明人： Tatsunori Kanai , Seiji Maeda , Hirokuni Yano , Kenichiro Yoshii
IPC分类号： G06F9/46 , G06F15/16 , G06F13/00 , H04L12/28
CPC分类号： G06F9/4881
摘要： An information processing system performs a plurality of tasks within a specific time interval. The system includes a bus, a plurality of processors which transfer data via the bus, and a unit for performing a scheduling operation of determining execution start timing of each of the tasks and at least one the processors which executes the tasks, based on cost information concerning a time required to perform each of the tasks and bandwidth information concerning a data transfer bandwidth required by each of the tasks, to perform the tasks within the specific time interval without overlapping execution terms of at least two tasks of the tasks, the two tasks requiring data transfer bandwidths not less than those of the others of the tasks.
摘要翻译：信息处理系统在特定时间间隔内执行多个任务。该系统包括总线，经由总线传送数据的多个处理器和用于执行确定每个任务的执行开始定时的调度操作的单元和至少一个执行任务的处理器，基于成本信息关于执行每个任务所需的时间和与每个任务所需的数据传输带宽有关的带宽信息，以在特定时间间隔内执行任务而不重叠任务的至少两个任务的执行条件，这两个任务要求数据传输带宽不低于其他任务的带宽。

30. 发明授权

US07657890B2 Scheduling system and method in which threads for performing a real-time operation are assigned to a plurality of processors 失效
标题翻译：将用于执行实时操作的线程分配给多个处理器的调度系统和方法
公开(公告)号：US07657890B2
公开(公告)日：2010-02-02
申请号：US10808470
申请日：2004-03-25
申请人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
发明人： Tatsunori Kanai , Seiji Maeda , Kenichiro Yoshii , Hirokuni Yano
IPC分类号： G06F9/46 , G06F12/00 , G06F9/26
CPC分类号： G06F9/50 , G06F9/45533
摘要： A real-time processing system that executes a plurality of threads, each of the threads being a unit of execution of a real-time operation, comprises a plurality of processors, a unit which selects a tightly coupled thread group from among the threads based on coupling attribute information indicative of a coupling attribute between the threads, the tightly coupled thread group including a set of tightly coupled threads running in cooperation with each other, and a unit which performs a scheduling operation of dispatching the tightly coupled threads to several of the processors that are equal to the tightly coupled threads to simultaneously execute the tightly coupled threads by the several of the processors.
摘要翻译：执行多个线程的实时处理系统，每个线程是执行实时操作的单元，包括多个处理器，一个单元，其基于以下方式从线程中选择紧密耦合的线程组：耦合属性信息，指示线程之间的耦合属性，紧密耦合的线程组包括彼此协作运行的一组紧密耦合的线程;以及单元，执行调度操作以将紧密耦合的线程分派到若干处理器这等于紧密耦合的线程，以同时由几个处理器执行紧密耦合的线程。

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