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21. 发明申请

US20080146039A1 METHOD TO REDUCE PLASMA CHARGE DAMAGE FROM HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP-CVD) PROCESS 审中-公开
标题翻译：降低高密度等离子体化学气相沉积（HDP-CVD）工艺的等离子体电荷损失的方法
公开(公告)号：US20080146039A1
公开(公告)日：2008-06-19
申请号：US11611212
申请日：2006-12-15
申请人： Daewon Yang , Jeffery B. Maxson , Ann N. McDonald
发明人： Daewon Yang , Jeffery B. Maxson , Ann N. McDonald
IPC分类号： H01L21/283
CPC分类号： C23C16/50
摘要： A method of processing wafers within a high density plasma chemical vapor deposition chamber comprises setting a plasma charge level within the chamber at a zero power level and, while the plasma charge level within the chamber is at the zero power level, moving a wafer into the chamber. Then, the method sets the plasma charge level to a second power level higher than zero after the wafer is moved into the chamber and performs a chemical vapor deposition process on the wafer within the chamber. After performing the chemical vapor deposition process, the method moves the wafer to a non-plasma region within the chamber. Then, after moving the wafer to the non-plasma region within the chamber, the method again sets the plasma charge level within the chamber at the zero power level. Next, after setting the plasma charge level within the chamber at the zero power level, the method opens the door of the chamber and, while the plasma charge level within the chamber is at the zero power level, the method removes the wafer from the chamber through the door of the chamber.
摘要翻译：在高密度等离子体化学气相沉积室内处理晶片的方法包括在零功率水平下设置室内的等离子体电荷水平，并且在室内的等离子体电荷水平处于零功率水平的同时，将晶片移动到房间。然后，该方法将晶片移入腔室之后，将等离子体电荷电平设置为高于零的第二功率电平，并在腔室内的晶片上执行化学气相沉积工艺。在执行化学气相沉积工艺之后，该方法将晶片移动到室内的非等离子体区域。然后，在将晶片移动到室内的非等离子体区域之后，该方法再次将室内的等离子体电荷水平设置在零功率水平。接下来，在将腔室内的等离子体充电水平设置在零功率水平之后，该方法打开腔室的门，并且在室内的等离子体充电水平处于零功率水平的同时，该方法将晶片从腔室通过房间的门。

22. 发明授权

US07179760B2 Bilayer cap structure including HDP/bHDP films for conductive metallization and method of making same 失效
标题翻译：双层盖结构，包括用于导电金属化的HDP / bHDP膜及其制造方法
公开(公告)号：US07179760B2
公开(公告)日：2007-02-20
申请号：US10908833
申请日：2005-05-27
申请人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Thomas F. Houghton , Michael F. Lofaro , Jeffery B. Maxson , Ann H. McDonald , Yun-Yu Wang , Keith Kwong Hon Wong , Daewon Yang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.
摘要翻译：本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层）选择性。

23. 发明授权

US06914015B2 HDP process for high aspect ratio gap filling 失效
标题翻译： HDP工艺用于高宽比间隙填充
公开(公告)号：US06914015B2
公开(公告)日：2005-07-05
申请号：US10605857
申请日：2003-10-31
申请人： Michael P. Belyansky , Patricia Argandona , Gregory DiBello , Andreas Knorr , Daewon Yang
发明人： Michael P. Belyansky , Patricia Argandona , Gregory DiBello , Andreas Knorr , Daewon Yang
IPC分类号： H01L21/314 , H01L21/316 , H01L21/318 , H01L21/762 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31625 , H01L21/31629 , H01L21/3185 , H01L21/76224 , H01L27/10844
摘要： An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.
摘要翻译：用于高纵横比间隙填充的HDP工艺包括在高密度等离子体条件下以低于约10毫托的第一压力使半导体衬底与氧化物前体接触，其中所述间隙部分地填充有氧化物; 并且在高密度等离子体条件下，在大于约10毫托的第二压力下进一步使基底与氧化物前体接触，其中所述间隙进一步用氧化物填充。

24. 发明授权

US09080239B2 Method and apparatus for angular high density plasma chemical vapor deposition 有权
标题翻译：用于角高密度等离子体化学气相沉积的方法和装置
公开(公告)号：US09080239B2
公开(公告)日：2015-07-14
申请号：US13434934
申请日：2012-03-30
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： C23C16/507 , C23C16/34 , C23C16/40 , C23C16/455 , C23C16/458 , C23C16/56 , H01J37/20 , H01J37/32 , H01L27/108 , H01L21/316 , H01L21/318
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

25. 发明授权

US07804136B2 Method of forming nitride films with high compressive stress for improved PFET device performance 有权
标题翻译：形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法
公开(公告)号：US07804136B2
公开(公告)日：2010-09-28
申请号：US11875217
申请日：2007-10-19
申请人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
发明人： Richard A. Conti , Ronald P. Bourque , Nancy R. Klymko , Anita Madan , Michael C. Smits , Roy H. Tilghman , Kwong Hon Wong , Daewon Yang
IPC分类号： H01L23/62
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.
摘要翻译：提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。这种压应力允许改进PFET中的器件性能。使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。氮化物层的厚度在约300-2000埃的范围内。

26. 发明授权

US07521307B2 CMOS structures and methods using self-aligned dual stressed layers 失效
标题翻译： CMOS结构和方法采用自对准双应力层
公开(公告)号：US07521307B2
公开(公告)日：2009-04-21
申请号：US11380695
申请日：2006-04-28
申请人： Huilong Zhu , Daewon Yang
发明人： Huilong Zhu , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/31116 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843
摘要： A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.
摘要翻译：用于制造CMOS结构的CMOS结构和方法提供了位于第一晶体管之上的第一应力层和位于第二晶体管上方的第二应力层邻接但不重叠。当在第一晶体管和第二晶体管之一内的源极/漏极区域上形成与硅化物层的接触时，这种不存在重叠的基台提供增强的制造灵活性。

27. 发明授权

US07514370B2 Compressive nitride film and method of manufacturing thereof 有权
标题翻译：压缩性氮化物膜及其制造方法
公开(公告)号：US07514370B2
公开(公告)日：2009-04-07
申请号：US11419217
申请日：2006-05-19
申请人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
发明人： Daewon Yang , Woo-Hyeong Lee , Tai-chi Su , Yun-Yu Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/3185 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.
摘要翻译：本发明的实施例提供一种通过高密度等离子体沉积工艺形成在衬底上产生的多个p型场效应晶体管栅极结构的压应力氮化物膜的形成方法。实施例包括使用至少硅烷，氩和氮的源气体产生填充有高密度等离子体的环境; 在0.8W / cm 2至5.0W / cm 2之间的范围内将衬底偏置为变化密度的高频功率; 以及将所述高密度等离子体沉积到所述多个栅极结构以形成所述压应力氮化物膜。

28. 发明申请

US20080173985A1 DIELECTRIC CAP HAVING MATERIAL WITH OPTICAL BAND GAP TO SUBSTANTIALLY BLOCK UV RADIATION DURING CURING TREATMENT, AND RELATED METHODS 审中-公开
标题翻译：具有光学带隙的材料的电介质板在固化处理期间实质性地阻挡紫外线辐射，以及相关方法
公开(公告)号：US20080173985A1
公开(公告)日：2008-07-24
申请号：US11626552
申请日：2007-01-24
申请人： Michael P. Belyansky , Griselda Bonilla , Xiao Hu Liu , Son Van Nguyen , Thomas M. Shaw , Hosadurga K. Shobha , Daewon Yang
发明人： Michael P. Belyansky , Griselda Bonilla , Xiao Hu Liu , Son Van Nguyen , Thomas M. Shaw , Hosadurga K. Shobha , Daewon Yang
IPC分类号： H01L23/58 , H01L21/318
CPC分类号： H01L21/02123 , H01L21/02126 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/02348 , H01L21/318 , H01L21/3185 , H01L21/76826 , H01L21/76828 , H01L21/76834
摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,
摘要翻译：公开了介电盖和相关方法。在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，

29. 发明申请

US20080045039A1 METHOD OF FORMING NITRIDE FILMS WITH HIGH COMPRESSIVE STRESS FOR IMPROVED PFET DEVICE PERFORMANCE 失效
公开(公告)号：US20080045039A1
公开(公告)日：2008-02-21
申请号：US11873721
申请日：2007-10-17
申请人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
发明人： Richard Conti , Ronald Bourque , Nancy Klymko , Anita Madan , Michael Smits , Roy Tilghman , Kwong Wong , Daewon Yang
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823828 , H01L29/7843
摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

30. 发明申请

US20070252230A1 CMOS STRUCTURES AND METHODS FOR IMPROVING YIELD 有权
标题翻译： CMOS结构和改进方法
公开(公告)号：US20070252230A1
公开(公告)日：2007-11-01
申请号：US11757792
申请日：2007-06-04
申请人： Huilong Zhu , Daewon Yang
发明人： Huilong Zhu , Daewon Yang
IPC分类号： H01L21/76 , H01L27/12
CPC分类号： H01L21/31116 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843
摘要： A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.
摘要翻译：提供了使用接触蚀刻阻挡衬垫（包括单中性应力衬垫，单应力衬垫和双应力衬垫（DSL））技术来提高CMOS器件产量的简单，有效和经济的方法。为了提高芯片产量，本发明提供了一种使用溅射蚀刻工艺来平滑/平坦化（即，薄）接触蚀刻止动衬片的顶表面的方法。当使用DSL技术时，本发明的溅射蚀刻工艺用于降低由DSL边界引起的DSL平滑/平坦化表面的复杂性，这导致显着的产量增加。本发明还提供了包括至少一个蚀刻衬里的半导体结构。

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