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21. 发明授权

US07863686B2 Nonvolatile memory devices having a fin shaped active region 失效
标题翻译：具有鳍形有源区域的非易失性存储器件
公开(公告)号：US07863686B2
公开(公告)日：2011-01-04
申请号：US12536740
申请日：2009-08-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/66
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

22. 发明申请

US20100317157A1 CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING THE SAME 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US20100317157A1
公开(公告)日：2010-12-16
申请号：US12850677
申请日：2010-08-05
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： H01L21/8239
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

23. 发明申请

US20090294837A1 Nonvolatile Memory Devices Having a Fin Shaped Active Region 失效
标题翻译：具有鳍形活动区域的非易失性存储器件
公开(公告)号：US20090294837A1
公开(公告)日：2009-12-03
申请号：US12536740
申请日：2009-08-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/792 , H01L29/78
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

24. 发明申请

US20080265307A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
公开(公告)号：US20080265307A1
公开(公告)日：2008-10-30
申请号：US12133858
申请日：2008-06-05
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11568 , H01L29/42324 , H01L29/42332 , H01L29/513 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

25. 发明申请

US20060180851A1 Non-volatile memory devices and methods of operating the same 审中-公开
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20060180851A1
公开(公告)日：2006-08-17
申请号：US11402389
申请日：2006-04-12
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： G11C16/12 , G11C16/14 , G11C16/26 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/40114 , H01L29/42332 , H01L29/513 , H01L29/7782 , H01L29/792 , H01L29/7923
摘要： Non-volatile memory devices and methods of operating the same are disclosed. A non-volatile memory device includes a semiconductor substrate. A tunnel insulating layer and a gate electrode are on the semiconductor substrate. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with a plurality of layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than a minimum field in the blocking insulation layer. A minimum field established at a blocking insulation layer can be stronger than a minimum field established at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than that of charges through the blocking insulation layer. Therefore, it may be possible to use lower operation voltages, obtain higher program and erase speeds, and/or obtain a greater difference between threshold values of a program threshold voltage and an erase threshold voltage. As a result, a multi-valued non-volatile memory device may be formed therefrom.
摘要翻译：公开了非易失性存储器件及其操作方法。非易失性存储器件包括半导体衬底。隧道绝缘层和栅电极位于半导体衬底上。具有多个层的多重隧道绝缘层，电荷存储绝缘层和具有多个层的多重阻挡绝缘层依次堆叠在栅电极和隧道绝缘层之间。半导体衬底中的第一扩散区域和第二扩散区域与栅电极的相对的相对侧相邻。当向栅电极和半导体衬底施加电压以形成其间的电压电平差时，隧道绝缘层中的最小场强比阻挡绝缘层中的最小场强。在阻挡绝缘层处建立的最小场强可以比在隧道绝缘层处建立的最小场强更强，并且通过隧道绝缘层的电荷的迁移概率可以高于通过阻挡绝缘层的电荷的迁移概率。因此，可以使用较低的操作电压，获得更高的编程和擦除速度，和/或获得程序阈值电压和擦除阈值电压的阈值之间的较大差异。结果，可以从其形成多值非易失性存储器件。

26. 发明授权

US06894924B2 Operating a non-volatile memory device 失效
标题翻译：操作非易失性存储设备
公开(公告)号：US06894924B2
公开(公告)日：2005-05-17
申请号：US10133684
申请日：2002-04-25
申请人： Jung-Dal Choi , Chang-Hyun Lee
发明人： Jung-Dal Choi , Chang-Hyun Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C16/14 , G11C16/26
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26
摘要： An operation method of programming, erasing, and reading a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device having a tunnel oxide layer thicker than 20 Å is provided. A program operation of the method is accomplished by applying a program voltage higher than 0 volts and a ground voltage to a gate electrode and a channel region of a selected SONOS cell transistor, respectively. Also, an erasing operation is accomplished by applying a ground voltage and a first erase voltage lower than 0 volts to a bulk region and a gate electrode of a selected SONOS cell transistor, respectively, and by applying a second erasure voltage to either a drain region or a source region of the selected SONOS cell transistor. The second erase voltage is a ground voltage or a positive voltage. In addition, a read operation is accomplished using either a backward read mode or a forward read mode. Thus, it is possible to remarkably improve a bake retention characteristic, which is sensitive to a thickness of the tunnel oxide layer.
摘要翻译：提供了一种编程，擦除和读取具有大于20埃的隧道氧化物层的氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储器件的操作方法。该方法的程序操作通过分别向所选择的SONOS单元晶体管的栅电极和沟道区施加高于0伏的编程电压和接地电压来实现。此外，擦除操作是通过分别对所选择的SONOS单元晶体管的体区域和栅电极施加接地电压和低于0伏特的第一擦除电压来实现的，并且通过向漏极区域施加第二擦除电压或所选择的SONOS单元晶体管的源极区域。第二擦除电压是接地电压或正电压。此外，使用反向读取模式或正向读取模式来实现读取操作。因此，可以显着提高对隧道氧化物层的厚度敏感的烘烤保持特性。

27. 发明授权

US08035151B2 Semiconductor device capable of suppressing short channel effect and method of fabricating the same 有权
标题翻译：能够抑制短路效应的半导体装置及其制造方法
公开(公告)号：US08035151B2
公开(公告)日：2011-10-11
申请号：US12382385
申请日：2009-03-16
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/11526 , H01L27/11529 , H01L27/11568 , H01L27/11573 , H01L29/1083
摘要： A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.
摘要翻译：半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。

28. 发明授权

US07968931B2 Non-volatile semiconductor memory devices 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07968931B2
公开(公告)日：2011-06-28
申请号：US12503354
申请日：2009-07-15
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11568 , H01L29/42324 , H01L29/42332 , H01L29/513 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.
摘要翻译：非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。电荷存储层位于隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。栅电极位于阻挡绝缘层上。

29. 发明授权

US07808036B2 Memory device and method of fabricating the same 有权
公开(公告)号：US07808036B2
公开(公告)日：2010-10-05
申请号：US11976389
申请日：2007-10-24
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

30. 发明授权

US07759723B2 Non-volatile semiconductor memory devices 有权
公开(公告)号：US07759723B2
公开(公告)日：2010-07-20
申请号：US12133858
申请日：2008-06-05
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11568 , H01L29/42324 , H01L29/42332 , H01L29/513 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

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