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21. 发明授权

US06867481B2 Lead frame structure with aperture or groove for flip chip in a leaded molded package 失效
标题翻译：引线框架结构，带引线模制封装中的倒装芯片的孔或凹槽
公开(公告)号：US06867481B2
公开(公告)日：2005-03-15
申请号：US10411688
申请日：2003-04-11
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L21/60 , H01L23/495 , H01L23/28
CPC分类号： H01L24/40 , H01L21/565 , H01L23/49503 , H01L23/49548 , H01L23/49562 , H01L24/37 , H01L24/81 , H01L2224/16 , H01L2224/16245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/81801 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/37099
摘要： A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.
摘要翻译：公开了一种半导体管芯封装。在一个实施例中，管芯封装包括包括第一表面和第二表面的半导体管芯，以及具有管芯附着区域的引线框架结构以及远离管芯附着区域延伸的多个引线。管芯附着区域包括一个或多个孔。成型材料围绕引线框架结构的芯片附接区域和半导体管芯的至少一部分。成型材料也在一个或多个孔内。

22. 发明申请

US20120181675A1 SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体芯片封装及其制造方法
公开(公告)号：US20120181675A1
公开(公告)日：2012-07-19
申请号：US13430347
申请日：2012-03-26
申请人： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , David Chong , Tan Teik Keng , Shibaek Nam , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Lay Yeap Lim , Byoung-Ok Lee
发明人： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , David Chong , Tan Teik Keng , Shibaek Nam , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Lay Yeap Lim , Byoung-Ok Lee
IPC分类号： H01L23/495
CPC分类号： H01L24/29 , H01L21/561 , H01L23/3121 , H01L23/4951 , H01L23/49558 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/32 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L2223/54406 , H01L2223/54486 , H01L2224/16 , H01L2224/291 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/293 , H01L2224/32057 , H01L2224/32225 , H01L2224/40245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/45565 , H01L2224/456 , H01L2224/45644 , H01L2224/45669 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49113 , H01L2224/4943 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/83801 , H01L2224/8385 , H01L2224/85013 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/19043 , H01L2924/30107 , H01L2224/85 , H01L2924/00 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2224/37099
摘要： Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
摘要翻译：公开了半导体管芯封装。示例性半导体管芯封装包括预成型衬底。预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

23. 发明授权

US07821124B2 Thin, thermally enhanced flip chip in a leaded molded package 有权
标题翻译：薄的，热增强的倒装芯片在有铅模制包装
公开(公告)号：US07821124B2
公开(公告)日：2010-10-26
申请号：US11961589
申请日：2007-12-20
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/48 , H01L23/495 , H01L23/34 , H01L29/76
CPC分类号： H01L23/495 , H01L23/49548 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/34 , H01L24/37 , H01L2224/16 , H01L2224/16245 , H01L2224/37599 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/37099
摘要： Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.
摘要翻译：公开了半导体管芯封装及其制造方法。示例性封装包括具有源极引线和栅极引线的引线框架，以及在引线框架的第一表面处耦合到源极和栅极引线的半导体管芯。源极引线在引线框架的第二表面具有突出区域。模塑材料设置在半导体管芯，栅极引线和源极引线周围，使得模具的表面和突出区域的表面被模制材料暴露。一种示例性方法包括获得半导体管芯和引线框架，以及在引线框架和管芯的至少一部分周围形成模制材料，使得突出区域的表面通过模制材料露出。

24. 发明申请

US20080105957A1 THIN, THERMALLY ENHANCED FLIP CHIP IN A LEADED MOLDED PACKAGE 有权
标题翻译：薄膜，热成型包装中的热成型芯片
公开(公告)号：US20080105957A1
公开(公告)日：2008-05-08
申请号：US11961589
申请日：2007-12-20
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/495
CPC分类号： H01L23/495 , H01L23/49548 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/34 , H01L24/37 , H01L2224/16 , H01L2224/16245 , H01L2224/37599 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/37099
摘要： Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
摘要翻译：本发明的实施例涉及半导体管芯封装。本发明的一个实施例涉及一种半导体管芯封装，其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构被耦合（c）栅极引线结构，其耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料，其中所述模制材料暴露所述半导体管芯的所述第二表面，以及源极引线结构的主表面。

25. 发明授权

US07335532B2 Method of assembly for multi-flip chip on lead frame on overmolded IC package 失效
标题翻译：包覆成型IC封装上引线框架上多重倒装芯片的组装方法
公开(公告)号：US07335532B2
公开(公告)日：2008-02-26
申请号：US11560935
申请日：2006-11-17
申请人： Jonathan A. Noquil , Seung Yong Choi , Rajeev Joshi , Chung-Lin Wu
发明人： Jonathan A. Noquil , Seung Yong Choi , Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L21/44
CPC分类号： H01L25/16 , H01L23/3128 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.
摘要翻译：多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

26. 发明申请

US20060284291A1 Lead frame structure with aperture or groove for flip chip in a leaded molded package 失效
公开(公告)号：US20060284291A1
公开(公告)日：2006-12-21
申请号：US11448962
申请日：2006-06-06
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L24/40 , H01L21/565 , H01L23/49503 , H01L23/49548 , H01L23/49562 , H01L24/37 , H01L24/81 , H01L2224/16 , H01L2224/16245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/81801 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/37099
摘要： A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

27. 发明授权

US07022548B2 Method for making a semiconductor die package 失效
标题翻译：制造半导体管芯封装的方法
公开(公告)号：US07022548B2
公开(公告)日：2006-04-04
申请号：US10744849
申请日：2003-12-22
申请人： Rajeev Joshi , Chung-Lin Wu
发明人： Rajeev Joshi , Chung-Lin Wu
IPC分类号： H01L21/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03442 , H01L2224/03462 , H01L2224/0347 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05184 , H01L2224/05559 , H01L2224/05572 , H01L2224/056 , H01L2224/05647 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/05124 , H01L2924/00014 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2924/013
摘要： A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.
摘要翻译：公开了一种处理半导体衬底的方法。该方法包括在具有导电区域的半导体衬底上提供具有孔的掩模。掩模中的孔设置在导电区上。将预先形成的导电柱放置在孔中并结合到导电区。

28. 发明申请

US20090032300A1 Method of and apparatus for providing an RF shield on an electronic component 有权
标题翻译：在电子部件上提供RF屏蔽的方法和装置
公开(公告)号：US20090032300A1
公开(公告)日：2009-02-05
申请号：US12221256
申请日：2008-07-31
申请人： Rajeev Joshi
发明人： Rajeev Joshi
IPC分类号： H05K9/00 , B05D5/12 , C23C14/34
CPC分类号： H05K9/0024 , H05K1/0218 , H05K3/284 , H05K3/4015 , H05K2201/10242 , H05K2203/041 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146
摘要： A shielding assembly is configured to provide electromagnetic shielding and environmental protection to one or more electronic components coupled to a substrate. The shielding assembly includes a non-conductive mold compound layer, such as a dielectric epoxy. The mold compound layer is applied to a top surface of the substrate, thereby covering the electronic components and providing protection against environmentally induced conditions such as corrosion, humidity, and mechanical stress. The shielding assembly also includes a conductive layer applied to a top surface of the mold compound layer. The conductive layer is coupled to a ground plane in the substrate, thereby enabling the electromagnetic shielding function. The conductive layer is coupled to the ground plane via one or more metallized contacts that are coupled to the substrate and extend through the mold compound layer.
摘要翻译：屏蔽组件被配置为向耦合到衬底的一个或多个电子部件提供电磁屏蔽和环境保护。屏蔽组件包括非导电模制化合物层，例如电介质环氧树脂。模具化合物层被施加到基板的顶表面，从而覆盖电子部件并且提供防止诸如腐蚀，湿度和机械应力的环境诱发条件的保护。屏蔽组件还包括施加到模具化合物层的顶表面的导电层。导电层耦合到衬底中的接地平面，从而实现电磁屏蔽功能。导电层通过一个或多个金属化触点耦合到接地平面，金属化触点耦合到衬底并延伸穿过模具化合物层。

29. 发明申请

US20070249092A1 Semiconductor die package including multiple dies and a common node structure 有权
标题翻译：半导体管芯封装包括多个管芯和一个共同的节点结构
公开(公告)号：US20070249092A1
公开(公告)日：2007-10-25
申请号：US11410504
申请日：2006-04-24
申请人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
发明人： Rajeev Joshi , Venkat Iyer , Jonathan Klein
IPC分类号： H01L21/00
CPC分类号： H01L23/49575 , H01L23/492 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/40245 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.
摘要翻译：公开了一种能够安装在母板上的半导体管芯封装。半导体管芯封装包括衬底和安装在衬底上的第一半导体管芯，其中第一半导体管芯包括第一垂直器件，第一垂直器件包括第一半导体管芯的相对表面处的第一输入区域和第一输出区域。半导体管芯封装包括安装在基板上的第二半导体管芯，其中第二半导体管芯包括第二垂直器件，该第二垂直器件包括在第二半导体管芯的相对表面处的第二输入区域和第二输出区域。基本上平面的导电节点夹将第一半导体管芯中的第一输出区域和第二半导体管芯中的第二输入区域电连通。第一半导体管芯和第二半导体管芯位于衬底和导电节点夹之间。

30. 发明授权

US07196313B2 Surface mount multi-channel optocoupler 有权
标题翻译：表面贴装多通道光电耦合器
公开(公告)号：US07196313B2
公开(公告)日：2007-03-27
申请号：US10817195
申请日：2004-04-02
申请人： Maria Clemens Y. Quinones , Rajeev Joshi
发明人： Maria Clemens Y. Quinones , Rajeev Joshi
IPC分类号： H01L31/00 , G02B27/00
CPC分类号： G02B6/4201 , H01L2224/48091 , H01L2224/48247 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/13055 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： An optocoupler package is disclosed. The optocoupler package includes a substrate comprising a leadframe and a molding compound, and a plurality of optocouplers, each optocoupler including (i) an optical emitter, (ii) an optical receiver, (iii) and an optically transmissive medium disposed between the optical emitter and optical receiver, where the optical emitter and the optical receiver are electrically coupled to the leadframe.
摘要翻译：公开了一种光耦合器封装。光耦合器包括包括引线框架和模制化合物的基板和多个光耦合器，每个光耦合器包括（i）光发射器，（ii）光接收器，（iii）和设置在光发射器和光接收器，其中光发射器和光接收器电耦合到引线框架。

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