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21. 发明授权

US5264387A Method of forming uniformly thin, isolated silicon mesas on an insulating substrate 失效
标题翻译：在绝缘基板上形成均匀薄的隔离硅台面的方法
公开(公告)号：US5264387A
公开(公告)日：1993-11-23
申请号：US966959
申请日：1992-10-27
申请人： Klaus D. Beyer , Mark A. Jaso , Subramanian S. Iyer , Scott R. Stiffler , James D. Warnock
发明人： Klaus D. Beyer , Mark A. Jaso , Subramanian S. Iyer , Scott R. Stiffler , James D. Warnock
IPC分类号： H01L21/304 , H01L21/306 , H01L21/76 , H01L21/762 , H01L27/12 , H01L21/302
CPC分类号： H01L21/3212 , H01L21/76264 , H01L21/76283 , Y10S438/977
摘要： A method comprising the steps of: providing a substrate including an insulator material having a generally planar surface; forming a plurality of mesas of a semiconductor material on the substrate surface, the plurality of mesas spaced by channels extending to the substrate surface, the plurality of mesas including device mesas and dummy mesas; forming a polish-stop structure of at least one selected material over the substrate surface in the channels; polishing the plurality of mesas and stopping on the polish-stop structure whereby the plurality of mesas have the same thickness as the polish-stop structure; and replacing the dummy mesas with an insulator material whereby to electrically isolate the device mesas.
摘要翻译：一种方法，包括以下步骤：提供包括具有大致平坦表面的绝缘体材料的基板; 在所述基板表面上形成半导体材料的多个台面，所述多个台面间隔开延伸到所述基板表面的通道，所述多个台面包括设备台面和虚拟台面; 在通道中的衬底表面上形成至少一种所选材料的抛光 - 停止结构; 抛光多个台面并在抛光 - 停止结构上停止，由此多个台面具有与抛光 - 停止结构相同的厚度; 并用绝缘体材料代替虚拟台面，从而使器件台面电隔离。

22. 发明授权

US5227658A Buried air dielectric isolation of silicon islands 失效
标题翻译：硅海岛的绝缘空气电介质隔离
公开(公告)号：US5227658A
公开(公告)日：1993-07-13
申请号：US781429
申请日：1991-10-23
申请人： Klaus D. Beyer , San-Mei Ku , Victor J. Silvestri , Andrie S. Yapsir
发明人： Klaus D. Beyer , San-Mei Ku , Victor J. Silvestri , Andrie S. Yapsir
IPC分类号： H01L21/76 , H01L21/764 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L21/764
摘要： A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.

23. 发明授权

US4944836A Chem-mech polishing method for producing coplanar metal/insulator films on a substrate 失效
标题翻译：用于在基板上制造共面金属/绝缘体膜的化学抛光方法
公开(公告)号：US4944836A
公开(公告)日：1990-07-31
申请号：US791860
申请日：1985-10-28
申请人： Klaus D. Beyer , William L. Guthrie , Stanley R. Makarewicz , Eric Mendel , William J. Patrick , Kathleen A. Perry , William A. Pliskin , Jacob Riseman , Paul M. Schaible , Charles L. Standley
发明人： Klaus D. Beyer , William L. Guthrie , Stanley R. Makarewicz , Eric Mendel , William J. Patrick , Kathleen A. Perry , William A. Pliskin , Jacob Riseman , Paul M. Schaible , Charles L. Standley
IPC分类号： H01L21/3205 , H01L21/304 , H01L21/3105 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/304 , H01L21/31053 , H01L21/32134 , H01L21/7684
摘要： A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier.In a second example a substrate having a patterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.
摘要翻译：公开了一种根据化学机械抛光技术在基底上产生共面金属/绝缘体膜的方法。在一个示例中，具有其上的介电材料的图案化绝缘层的衬底被涂覆有金属层。然后将基板放置在平行的抛光机中，并将金属除去在其中保持完整的孔中除去。这通过使用改进的选择性浆料成为可能，其比电介质材料更快地除去金属。然后可以将绝缘层用作自动蚀刻停止屏障。在第二实施例中，具有图案化金属层的基板涂覆有绝缘层，然后进行化学研磨。该结构通过从结构的高点以比从较低点更快的速率化学去除绝缘材料而被共面化。也可以使用可选的蚀刻停止层。

24. 发明授权

US4758531A Method of making defect free silicon islands using SEG 失效
标题翻译：使用SEG制造无缺陷硅岛的方法
公开(公告)号：US4758531A
公开(公告)日：1988-07-19
申请号：US111888
申请日：1987-10-23
申请人： Klaus D. Beyer , Louis L. Hsu , Dominic J. Schepis , Victor J. Silvestri
发明人： Klaus D. Beyer , Louis L. Hsu , Dominic J. Schepis , Victor J. Silvestri
IPC分类号： H01L21/205 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76294 , Y10S148/026 , Y10S148/029 , Y10S148/097
摘要： A method for forming epitaxial grown silicon structure having substantially defect free outer surfaces and resulting structure is provided. A silicon substrate is provided, on which an epitaxial silicon crystal is grown. The outer surface layer of the silicon epitaxially grown silicon crystal will contain defective material which is removed by oxidation of the outer layer to silicon dioxide. This removes the defect containing outer layer, creating a new outer layer which is substantially defect free.

25. 发明授权

US4745081A Method of trench filling 失效
公开(公告)号：US4745081A
公开(公告)日：1988-05-17
申请号：US793518
申请日：1985-10-31
申请人： Klaus D. Beyer , Victor J. Silvestri
发明人： Klaus D. Beyer , Victor J. Silvestri
IPC分类号： H01L21/76 , H01L21/225 , H01L21/74 , H01L21/763 , H01L29/41 , H01L21/36 , H01L21/425
CPC分类号： H01L21/763 , H01L21/2255 , H01L21/743
摘要： A method of simultaneously producing doped silicon filled trenches in areas where a substrate contact is to be produced and trench isolation in other areas. Borosilicate glass lines the sidewalls of those trenches where a contact is desired and undoped epitaxially grown silicon fills all the trenches. Subsequent heat processing causes the boron in the borosilicate to dope the epitaxial silicon in those trenches. In the other trenches, the silicon fill remains undoped except at the bottom where a channel stop exists, thereby forming isolation trenches. The contacts formed over the trenches may be formed by selectively deposition of a highly doped silicon into an opening that overlies a portion of the trench and the adjacent substrate surface.

26. 发明授权

US4680614A Planar void free isolation structure 失效
标题翻译：平面无空隙隔离结构
公开(公告)号：US4680614A
公开(公告)日：1987-07-14
申请号：US711554
申请日：1985-03-14
申请人： Klaus D. Beyer , Victor J. Silvestri
发明人： Klaus D. Beyer , Victor J. Silvestri
IPC分类号： H01L21/20 , H01L21/74 , H01L21/763 , H01L21/95 , H01L27/04
CPC分类号： H01L21/743 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/763 , Y10S148/05 , Y10S148/085 , Y10S148/122 , Y10S148/131
摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.
摘要翻译：描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。第一绝缘层位于沟槽的侧壁上。沟槽的底部或底部对单晶半导体体是开放的。从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。沟槽宽度x的优选范围为约10微米或更小。多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。密封的外延单晶半导体防止在沟槽图案内形成空隙。外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

27. 发明授权

US4333794A Omission of thick Si.sub.3 N.sub.4 layers in ISA schemes 失效
标题翻译：在ISA方案中省略厚的Si3N4层
公开(公告)号：US4333794A
公开(公告)日：1982-06-08
申请号：US251698
申请日：1981-04-07
申请人： Klaus D. Beyer , Joseph S. Logan
发明人： Klaus D. Beyer , Joseph S. Logan
IPC分类号： H01L29/73 , H01L21/033 , H01L21/205 , H01L21/265 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/331 , H01L21/76 , H01L21/762 , H01L29/732 , H01L21/306 , H01L21/312
CPC分类号： H01L21/76232 , H01L21/033 , H01L21/76229 , H01L29/7325 , Y10S148/131
摘要： The present invention provides a process which comprises:(a) producing an ion-implantation resistant island on a substrate;(b) growing ion-implantation resistant sidewalls on the island;(c) implanting a first impurity;(d) removing the sidewalls;(e) implanting a second impurity where the sidewalls were;(f) growing a conformal etchable coating over the surface of the device;(g) masking to define an area spaced from and exterior to the area where the sidewalls were;(h) removing the conformal etchable coating in the area of step (g);(i) etching a deep trench in the area where the conformal coating was removed;(j) implanting a third impurity into the deep trench.Following island removal, the emitter and base of a bipolar transistor are formed in the area where the island existed.
摘要翻译：本发明提供了一种方法，其包括：（a）在基板上产生抗离子注入抗岛; （b）在岛上生长离子注入阻力侧壁; （c）植入第一杂质; （d）去除侧壁; （e）在侧壁处植入第二杂质; （f）在装置表面上生长保形蚀刻涂层; （g）掩蔽以限定与侧壁区域隔开并在其外部的区域; （h）在步骤（g）的区域中去除保形蚀刻涂层; （i）蚀刻去除保形涂层的区域中的深沟槽; （j）将第三杂质注入到深沟槽中。随着岛去除，双极晶体管的发射极和基极形成在岛存在的区域中。

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