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21. 发明授权

US5917743A Content-addressable memory (CAM) for a FLASH memory array 失效
标题翻译： FLASH存储器阵列的内容寻址存储器（CAM）
公开(公告)号：US5917743A
公开(公告)日：1999-06-29
申请号：US953714
申请日：1997-10-17
申请人： Anirban Roy
发明人： Anirban Roy
IPC分类号： G11C15/04 , G11C16/04 , G11C7/00
CPC分类号： G11C16/0491 , G11C15/046
摘要： A content addressable memory (CAM) cell for a FLASH memory array includes four multiple-row columns of FLASH cells formed in a virtual ground architecture having a single diffusion between neighboring columns of cells. The first column has isolation elements therein and the third column has the same data value stored in each FLASH cell thereof. The CAM cell also includes elements for providing read and source voltages to the third column.
摘要翻译：用于闪速存储器阵列的内容可寻址存储器（CAM）单元包括在虚拟地面架构中形成的四列多列FLASH单元，其具有相邻列单元之间的单个扩散。第一列在其中具有隔离元件，并且第三列具有存储在其每个闪存单元中的相同数据值。 CAM单元还包括用于向第三列提供读取和源极电压的元件。

22. 发明申请

US20150371711A1 CONTROL GATE DRIVER FOR USE WITH SPLIT GATE MEMORY CELLS 有权
标题翻译：控制门驱动器用于分离栅格存储器单元
公开(公告)号：US20150371711A1
公开(公告)日：2015-12-24
申请号：US14310585
申请日：2014-06-20
申请人： Jon S. Choy , Anirban Roy
发明人： Jon S. Choy , Anirban Roy
IPC分类号： G11C16/24 , G11C16/34 , G11C16/12 , G11C16/26 , G11C16/22
CPC分类号： G11C16/24 , G11C16/12 , G11C16/225 , G11C16/26 , G11C16/3445 , G11C16/3459
摘要： A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate.
摘要翻译：用于驱动分闸器非易失性存储单元的控制栅极的电路可以包括开关电流源; 第一晶体管，其具有耦合到所述开关电流源的电流电极和耦合到电压源的控制电极; 第二晶体管，其具有耦合到所述开关电流源的第二节点的电流电极，以及耦合到第三电压源的控制电极; 第三晶体管，其具有耦合到所述第二晶体管的控制电极，耦合到所述第一晶体管的电流电极和第四开关电压源; 以及第四晶体管，其具有耦合到所述第一开关电压源的电流电极，耦合到所述开关电流源的控制电极和在驱动器电压节点处耦合到所述第二晶体管的第二电流电极，其中所述驱动器电压节点可操作以驱动控制门。

23. 发明申请

US20120108932A1 GLUCOSE SENSOR SIGNAL PURITY ANALYSIS 有权
标题翻译：葡萄糖传感器信号纯度分析
公开(公告)号：US20120108932A1
公开(公告)日：2012-05-03
申请号：US12914963
申请日：2010-10-28
申请人： Anirban Roy
发明人： Anirban Roy
IPC分类号： A61B5/145
CPC分类号： A61B5/7221 , A61B5/14532 , A61B5/14865 , A61B5/4839 , A61B5/6849 , A61B5/7203 , A61M5/1723 , G01N33/48
摘要： Disclosed are methods, apparatuses, etc. for glucose sensor signal purity analysis. In certain example embodiments, a series of samples of at least one sensor signal that is responsive to a blood glucose level of a patient may be obtained. Based at least partly on the series of samples, at least one metric may be determined to characterize one or more non-physiological anomalies of a representation of the blood glucose level of the patient by the at least one sensor signal. A reliability of the at least one sensor signal to represent the blood glucose level of the patient may be assessed based at least partly on the at least one metric. Other example embodiments are disclosed herein.
摘要翻译：公开了葡萄糖传感器信号纯度分析的方法，装置等。在某些示例性实施例中，可以获得响应于患者的血糖水平的至少一个传感器信号的一系列样本。至少部分地基于所述一系列样本，可以确定至少一个度量来表征由所述至少一个传感器信号表示所述患者的血糖水平的一个或多个非生理异常。可以至少部分地基于至少一个度量来评估用于表示患者的血糖水平的至少一个传感器信号的可靠性。本文公开了其它示例性实施例。

24. 发明申请

US20110208155A1 CLOSED-LOOP GLUCOSE CONTROL STARTUP 有权
标题翻译：闭环葡萄糖控制启动
公开(公告)号：US20110208155A1
公开(公告)日：2011-08-25
申请号：US12709437
申请日：2010-02-19
申请人： Cesar C. Palerm , Anirban Roy
发明人： Cesar C. Palerm , Anirban Roy
IPC分类号： A61M31/00
CPC分类号： G06F19/3456 , G06F19/00
摘要： Disclosed are methods, systems, etc. for closed-loop glucose control startup. In certain example embodiments, a request for entry of an automatic mode of operation of a glucose monitoring and insulin delivery system for a patient may be detected. An entry of the automatic mode of operation may be controlled based, at least in part, on a detected rate of change of blood glucose concentration of the patient. In certain other example embodiments, initiation of a continual phase of an automatic mode of operation may be controlled based, at least in part, on a time since a most recent manual delivery of a bolus, on a detected rate of change of blood glucose concentration, on a targeted fixed set point, a combination thereof, and so forth.
摘要翻译：公开了用于闭环葡萄糖控制启动的方法，系统等。在某些示例性实施例中，可以检测到用于输入用于患者的葡萄糖监测和胰岛素递送系统的自动操作模式的请求。可以至少部分地基于检测到的患者血糖浓度的变化率来控制自动操作模式的输入。在某些其它示例性实施例中，可以至少部分地基于最近一次手动递送大剂量的时间，基于检测到的血糖浓度的变化率来控制自动操作模式的连续相的启动，在目标固定设定点上，其组合等。

25. 发明授权

US09318501B2 Methods and structures for split gate memory cell scaling with merged control gates 有权
标题翻译：具有合并控制门的分离栅极存储单元缩放的方法和结构
公开(公告)号：US09318501B2
公开(公告)日：2016-04-19
申请号：US14303290
申请日：2014-06-12
申请人： Anirban Roy , Ko-Min Chang
发明人： Anirban Roy , Ko-Min Chang
IPC分类号： H01L27/115 , H01L21/28 , H01L29/423 , H01L29/66
CPC分类号： H01L29/42348 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.
摘要翻译：存储器件具有在衬底中和之上的第一和第二存储器单元。第一掺杂区域处于第一有源区。第一有源区的顶表面与第一掺杂区的顶表面基本共面。控制栅极在第一掺杂区域之上，并且在第一掺杂区域的第一侧上并且在第一掺杂区域的第二侧上延伸。第一控制栅极和第一有源区域之间的电荷存储层包括在第一选择栅极和第一掺杂区域之间。第一选择栅极在第一掺杂区域的第一侧上并与控制栅极相邻的第一有源区上方。第二选择栅极位于第一掺杂区域的第二侧上并与控制栅极相邻的第一有源区上。

26. 发明授权

US09318496B2 Nonvolatile memory device with layout to minimize void formation and method of making the same 有权
标题翻译：具有布局的非易失性存储器件，以最小化空隙形成及其制造方法
公开(公告)号：US09318496B2
公开(公告)日：2016-04-19
申请号：US14194938
申请日：2014-03-03
申请人： Anirban Roy
发明人： Anirban Roy
IPC分类号： H01L27/115 , H01L27/02 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/0207 , H01L27/11519 , H01L29/7881
摘要： A memory device can include an array of NOR memory cells, each memory cell including a floating gate, a source on a source side of the floating gate, a drain on a drain side of the floating gate, a drain contact on the drain, and a source contact on the source. The source contacts are connected to a common source line. A plurality of bit lines are connected to respective drains in a column of the memory cells. A plurality of word lines, each word line coupled to respective floating gates in a row of the memory cells. Spacing between the word lines on the drain side is greater than spacing between the word lines on the source side.
摘要翻译：存储器件可以包括NOR存储器单元的阵列，每个存储器单元包括浮置栅极，浮置栅极的源极侧的源极，浮置栅极的漏极侧的漏极，漏极上的漏极接触，以及来源的源联系人。源触点连接到公共源极线。多个位线连接到存储器单元的列中的相应的漏极。多个字线，每个字线耦合到一行存储器单元中的相应浮动栅极。漏极侧的字线之间的间距大于源极上的字线之间的间距。

27. 发明授权

US09089292B2 Calibration of glucose monitoring sensor and/or insulin delivery system 有权
标题翻译：葡萄糖监测传感器和/或胰岛素输送系统的校准
公开(公告)号：US09089292B2
公开(公告)日：2015-07-28
申请号：US12748341
申请日：2010-03-26
申请人： Anirban Roy , Barry Keenan , Michael Kremliovsky
发明人： Anirban Roy , Barry Keenan , Michael Kremliovsky
IPC分类号： A61B5/00 , A61B5/145 , A61B5/1486 , A61B5/1495
CPC分类号： A61B5/1495 , A61B5/1451 , A61B5/14532 , A61B5/14865 , A61B5/4839 , A61B5/6849 , A61B5/7203 , A61B5/7221 , A61B5/725 , A61B5/7275 , A61B2560/0223 , A61M5/1723 , A61M2005/1726
摘要： Disclosed are methods, apparatuses, etc. for calibrating glucose monitoring sensors and/or insulin delivery systems. In certain example embodiments, blood glucose reference samples may be correlated with sensor measurements with regard to a delay associated with the sensor measurements. In certain other example embodiments, one or more parameters of a probability model may be estimated based on blood glucose reference sample-sensor measurement pairs. Based on such information, function(s) for estimating a blood-glucose concentration in a patient may be determined.
摘要翻译：公开了用于校准葡萄糖监测传感器和/或胰岛素递送系统的方法，装置等。在某些示例性实施例中，血糖参考样本可以与关于与传感器测量相关联的延迟的传感器测量值相关。在某些其他示例实施例中，可以基于血糖参考样本 - 传感器测量对来估计概率模型的一个或多个参数。基于这样的信息，可以确定用于估计患者血糖浓度的功能。

28. 发明授权

US07228132B2 Method and apparatus for providing service profile upgrades with minimal downtime 有权
标题翻译：以最少的停机时间提供服务配置文件升级的方法和设备
公开(公告)号：US07228132B2
公开(公告)日：2007-06-05
申请号：US11157230
申请日：2005-06-20
申请人： Saikrishnan Gopalakrishnan , Nachiket J. Deshpande , Anirban Roy , Sunil Kumar Chandrupatla
发明人： Saikrishnan Gopalakrishnan , Nachiket J. Deshpande , Anirban Roy , Sunil Kumar Chandrupatla
IPC分类号： H04Q7/20 , H04M3/42
CPC分类号： H04L41/5064 , H04L63/102 , H04L63/20 , H04L67/14 , H04L67/30
摘要： Methods and apparatus are disclosed for dynamically updating service profiles in a network system. A device, such as an edge device providing network services to subscribers, is configured to dynamically update profiles for services provided to subscribers with no downtime required. Devices may be configured in accordance with this disclosure to receive a request by a first subscriber to access a network service having an associated service profile. The device may then cache the current version of the service profile into memory. Upon receiving a request from a second subscriber to access the same network service, the device may then determine whether a newer version of the service profile exists. If a newer version exists, then the device may then associate the newer version of the service profile to the second subscriber's session. Older versions may be purged as they are no longer used.
摘要翻译：公开了用于在网络系统中动态更新服务简档的方法和装置。诸如向订户提供网络服务的边缘设备的设备被配置为动态地更新提供给订户的服务的配置文件，而不需要停机时间。可以根据本公开来配置设备，以接收第一订户访问具有相关服务简档的网络服务的请求。然后，设备可以将服务简档的当前版本缓存到存储器中。当接收到来自第二用户的访问相同网络服务的请求时，设备可以确定是否存在服务简档的较新版本。如果存在较新版本，则设备然后可以将服务简档的较新版本与第二用户的会话相关联。较旧的版本可能被清除，因为它们不再使用。

29. 发明授权

US06856542B2 Programmable logic device circuit and method of fabricating same 有权
标题翻译：可编程逻辑器件电路及其制造方法
公开(公告)号：US06856542B2
公开(公告)日：2005-02-15
申请号：US10164245
申请日：2002-06-04
申请人： Anirban Roy , Luca Giovanni Fasoli
发明人： Anirban Roy , Luca Giovanni Fasoli
IPC分类号： H01L21/82 , G11C14/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1736 , H01L27/115 , H01L27/11521 , H01L27/11803
摘要： A programmable logic device (PLD) and method for fabricating the PLD are disclosed. The PLD includes an array of PLD cells. Each PLD cell may include a programmable transistor and a select transistor. The PLD array is divided into at least one first area and at least one second area adjacent the at least one first area. The at least one first area includes the programmable transistors and the at least one second area includes the select transistors.
摘要翻译：公开了一种用于制造PLD的可编程逻辑器件（PLD）和方法。 PLD包括一系列PLD细胞。每个PLD单元可以包括可编程晶体管和选择晶体管。 PLD阵列被分成至少一个第一区域和与该至少一个第一区域相邻的至少一个第二区域。所述至少一个第一区域包括可编程晶体管，并且所述至少一个第二区域包括所述选择晶体管。

30. 发明授权

US5557124A Flash EEPROM and EPROM arrays with select transistors within the bit line pitch 失效
公开(公告)号：US5557124A
公开(公告)日：1996-09-17
申请号：US212176
申请日：1994-03-11
申请人： Anirban Roy , Reza Kazerounian
发明人： Anirban Roy , Reza Kazerounian
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： Flash EEPROM array and EPROM arrays are described. The EEPROM array has EEPROM areas with arrays of EEPROM transistors, at least one control area per EEPROM area and columns of a first polysilicon layer traversing the EEPROM and control areas. The columns are divided into even and odd columns. Each control area is divided into upper, middle and lower areas and each control area includes the following: a) within the middle area, cross-lines of the first polysilicon extending from each even to the next odd column; b) four rows of a second polysilicon layer, laid down after the columns and cross-lines of the first polysilicon layer within the control areas are removed; and c) isolating oxide elements laid down prior to the first polysilicon layer and self-aligned to it before it is removed. The isolating oxide elements are located under every odd column in the upper area, under each column in the middle area, under each odd column in one row of the lower area and under each even column in the other row of the lower area. Bit line select and erase select rows are in the upper and middle areas, respectively, and two column select rows are in the lower area. Erase select transistors are formed at the intersections of the removed cross-lines with the erase select row of second polysilicon, bit line select transistors are formed at the intersections of removed even columns with the bit line select row of second polysilicon, and column select transistors are formed at intersections of the column select rows of second polysilicon with the removed columns wherever no isolating oxide elements exist. The EPROM array has a similar structure but does not include the erase select transistors. The select transistors are n-channel transistors each formed of a) a channel, b) two diffusion bit lines bordering the channel and aligned to a first, subsequently removed, polysilicon layer and c) a second polysilicon layer extending between and over the two diffusion bit lines.

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