专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06424040B1 Integration of fluorinated dielectrics in multi-level metallizations 有权
标题翻译：氟化电介质在多层金属化中的集成
公开(公告)号：US06424040B1
公开(公告)日：2002-07-23
申请号：US09244586
申请日：1999-02-04
申请人： Somnath S. Nag , Changming Jin , Wei-Yung Hsu , Guoqiang Xing
发明人： Somnath S. Nag , Changming Jin , Wei-Yung Hsu , Guoqiang Xing
IPC分类号： H01L2348
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： Deposition of titanium over fluoride-containing dielectrics requires the use of a method of passivation to prevent the formation of TiF4, which causes delamination of the metallization structure. Disclosed methods include the formation of layers of Al203, TiN, or Si3N4.
摘要翻译：在含氟化物的电介质上沉积钛需要使用钝化方法来防止形成TiF 4，这导致金属化结构的分层。公开的方法包括形成Al 2 O 3，TiN或Si 3 N 4的层。

22. 发明授权

US07745335B2 Semiconductor device manufactured by reducing hillock formation in metal interconnects 有权
标题翻译：通过减少金属互连中的小丘形成制造的半导体器件
公开(公告)号：US07745335B2
公开(公告)日：2010-06-29
申请号：US11614511
申请日：2006-12-21
申请人： Ju-Ai Ruan , Changming Jin , Sopa Chevacharoenkul , Satyavolu Papa Rao , Tae Seung Kim
发明人： Ju-Ai Ruan , Changming Jin , Sopa Chevacharoenkul , Satyavolu Papa Rao , Tae Seung Kim
IPC分类号： H01L21/4763 , H01L21/44 , B05D3/00
CPC分类号： H01L21/02074 , H01L21/76883 , Y10S438/937
摘要： A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.
摘要翻译：一种制造互连结构的方法，包括将空的沉积室暴露于在等离子体存在下产生由源气体产生的反应物质的方法。该方法还包括终止等离子体，然后将其上的金属层的半导体衬底引入室中，同时反应物质存在于室中。

23. 发明授权

US07187080B2 Semiconductor device with a conductive layer including a copper layer with a dopant 有权
标题翻译：具有包括具有掺杂剂的铜层的导电层的半导体器件
公开(公告)号：US07187080B2
公开(公告)日：2007-03-06
申请号：US10964963
申请日：2004-10-14
申请人： Qing-Tang Jiang , Changming Jin , Joseph D. Luttmer
发明人： Qing-Tang Jiang , Changming Jin , Joseph D. Luttmer
IPC分类号： H01L23/48
CPC分类号： H01L21/76844 , H01L21/76849 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76888
摘要： A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.
摘要翻译：一种制造半导体器件的方法包括以下步骤：提供半导体衬底（202），在半导体衬底（202）上形成电介质层（204），并蚀刻电介质层（204）中的沟槽或通孔（206））以暴露半导体衬底（202）的表面的一部分。该方法还包括在沟槽或通孔（206）内形成导电层（212,220）的步骤。该方法还包括以下步骤：抛光导电层（220）的一部分并在预定温度下退火导电层（212,220）。此外，导电层（212,220）还包括掺杂剂，并且掺杂剂基本上扩散到导电层（212,220）的顶侧的表面，以形成掺杂剂氧化物层（212a，220a），当导电层（212,220）在预定温度下退火，掺杂剂暴露于氧气。

24. 发明授权

US07037823B2 Method to reduce silanol and improve barrier properties in low k dielectric ic interconnects 有权
标题翻译：在低k电介质互连中减少硅烷醇并改善阻隔性能的方法
公开(公告)号：US07037823B2
公开(公告)日：2006-05-02
申请号：US10901708
申请日：2004-07-27
申请人： Phillip D. Matz , Sameer Ajmera , Changming Jin , Trace Q. Hurd
发明人： Phillip D. Matz , Sameer Ajmera , Changming Jin , Trace Q. Hurd
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/02052 , H01L21/3105 , H01L21/31058 , H01L21/31116 , H01L21/31138 , H01L21/7682
摘要： A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.
摘要翻译：在形成在硅衬底（10）上的低k电介质层（100）中形成沟槽和通孔结构。超临界CO 2和第一甲硅烷基化剂用于形成化学键合的高密度表面层（160）。使用超临界CO 2和第二甲硅烷化剂从低k电介质层（100）除去硅烷醇物质。阻挡层（190）和铜（200）用于填充沟槽和通孔结构。

25. 发明授权

US06838300B2 Chemical treatment of low-k dielectric films 有权
标题翻译：低k电介质薄膜的化学处理
公开(公告)号：US06838300B2
公开(公告)日：2005-01-04
申请号：US10357560
申请日：2003-02-04
申请人： Changming Jin , Phillip D. Matz , Heungsoo Park , Patricia B. Smith , Andrew J. McKerrow
发明人： Changming Jin , Phillip D. Matz , Heungsoo Park , Patricia B. Smith , Andrew J. McKerrow
IPC分类号： H01L21/3065 , H01L21/033 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/00
CPC分类号： H01L21/0214 , H01L21/02126 , H01L21/02131 , H01L21/02321 , H01L21/02332 , H01L21/0234 , H01L21/0332 , H01L21/3105 , H01L21/31629 , H01L21/76826 , H01L21/76828 , H01L21/76829
摘要： A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer (40) formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (40), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer (40).
摘要翻译：公开了一种形成集成电路的方法，该集成电路包括由有机硅酸盐玻璃等取代基贫氧化硅形成的有机硅酸盐低介电常数绝缘层（40）。已经观察到随后的等离子体处理破坏了这种绝缘层（40）中的结合，从而导致具有悬挂键的膜表面的分子。最终，损坏的绝缘层（40）包括硅烷醇分子，这导致膜的退化。所公开的方法将损坏的绝缘层（40）暴露于热或等离子体活化的氟，氢或氮，其与损坏的分子反应以形成绝缘层（40）的钝化表面。

26. 发明授权

US06800928B1 Porous integrated circuit dielectric with decreased surface porosity 失效
标题翻译：多孔集成电路电介质具有降低的表面孔隙率
公开(公告)号：US06800928B1
公开(公告)日：2004-10-05
申请号：US09087234
申请日：1998-05-28
申请人： Wei William Lee , Richard Scott List , Changming Jin
发明人： Wei William Lee , Richard Scott List , Changming Jin
IPC分类号： H01L2358
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76224 , H01L21/76819 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76837 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).
摘要翻译：用于多孔二氧化硅的表面处理以增强上覆层的粘附力。处理包括侵入干凝胶（510）的开放表面孔（514）的表面取代，孔塌陷和间隙填充层（520）。

27. 发明授权

US06784121B1 Integrated circuit dielectric and method 有权
标题翻译：集成电路电介质和方法
公开(公告)号：US06784121B1
公开(公告)日：2004-08-31
申请号：US09178249
申请日：1998-10-23
申请人： Changming Jin , Richard Scott List , Joseph D. Luttmer
发明人： Changming Jin , Richard Scott List , Joseph D. Luttmer
IPC分类号： H01L2131
CPC分类号： H01L23/53295 , C23C18/1212 , C23C18/122 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/0234 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/3105 , H01L21/31695 , H01L21/76819 , H01L21/7682 , H01L21/76825 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L21/76837 , H01L23/522 , H01L23/5222 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.
摘要翻译：干凝胶老化系统包括具有入口和出口的老化室（190），并且将气相中的凝胶催化剂在半导体晶片上的干凝胶前体膜上流动。优选的实施方案使用氨和水蒸气混合催化剂。

28. 发明授权

US06723636B1 Methods for forming multiple damascene layers 有权
标题翻译：形成多个镶嵌层的方法
公开(公告)号：US06723636B1
公开(公告)日：2004-04-20
申请号：US10447513
申请日：2003-05-28
申请人： Noel M. Russell , Kenneth Joseph Newton , Changming Jin
发明人： Noel M. Russell , Kenneth Joseph Newton , Changming Jin
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L21/7681 , H01L2221/1031
摘要： According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.
摘要翻译：根据本发明的一个实施例，提供了一种用于形成半导体器件的多层的方法。该方法包括通过覆盖在第一层上的电介质层限定通孔。第一层包括至少部分地位于通孔下方的导电部分。该方法还包括用电介质材料过填充通孔以形成覆盖在电介质层上的第二层。该方法还包括通过蚀刻穿过第二层和通孔中的介电材料形成连接到通孔的沟槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式