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21. 发明授权

US07474587B2 Flash memory device with rapid random access function and computing system including the same 有权
标题翻译：具有快速随机存取功能和计算系统的闪存设备包括相同的功能
公开(公告)号：US07474587B2
公开(公告)日：2009-01-06
申请号：US11673996
申请日：2007-02-12
申请人： Chi-Weon Yoon
发明人： Chi-Weon Yoon
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C16/26
摘要： A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read circuit configured to sense data from the memory cell array in response to an address output from the address buffer circuit, an output data latch circuit configured to receive data sensed by the read circuit, and a control logic coupled to the address buffer circuit, the read circuit, and the output data latch circuit, and configured to control the output data latch circuit and the read circuit such that the output data latch circuit outputs first data read from the memory cell array substantially simultaneously as the read circuit senses second data from the memory cell array.
摘要翻译：闪速存储器件包括存储单元阵列，包括地址缓冲器的地址缓冲器电路，每个地址缓冲器被配置为存储用于随机读取操作的地址;读取电路，被配置为响应于地址输出来检测来自存储器单元阵列的数据从所述地址缓冲电路输出的数据锁存电路被配置为接收由所述读取电路感测的数据，以及控制逻辑，其耦合到所述地址缓冲器电路，所述读取电路和所述输出数据锁存电路，并且被配置为控制所述输出数据锁存电路和读取电路，使得当读取电路从存储器单元阵列感测到第二数据时，输出数据锁存电路基本上同时输出从存储单元阵列读取的第一数据。

22. 发明授权

US07433244B2 Flash memory device and related erase operation 有权
标题翻译：闪存设备和相关擦除操作
公开(公告)号：US07433244B2
公开(公告)日：2008-10-07
申请号：US11501070
申请日：2006-08-09
申请人： Chi-Weon Yoon , Heung-Soo Lim
发明人： Chi-Weon Yoon , Heung-Soo Lim
IPC分类号： G11C16/00
CPC分类号： G11C16/16 , G11C16/3409 , G11C16/345 , G11C16/3477
摘要： An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.
摘要翻译：闪存器件的擦除操作包括基于地址识别包括多个扇区的扇区组，同时对扇区组中的扇区进行预编程，同时擦除扇区组，并同时对扇区进行后编程行业组。

23. 发明授权

US09851912B2 Memory device, memory system and method of operating memory device 有权
公开(公告)号：US09851912B2
公开(公告)日：2017-12-26
申请号：US15443647
申请日：2017-02-27
申请人： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
发明人： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
IPC分类号： G11C11/34 , G11C16/04 , G06F3/06
CPC分类号： G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
摘要： A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

24. 发明授权

US09589632B2 Resistive memory device including column decoder and method of performing a bidirectional driving operation and providing appropriate biasing with respect to bit lines 有权
标题翻译：电阻式存储器件包括列译码器和执行双向驱动操作并提供相对于位线的适当偏置的方法
公开(公告)号：US09589632B2
公开(公告)日：2017-03-07
申请号：US14820197
申请日：2015-08-06
申请人： Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
发明人： Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C11/22
CPC分类号： G11C13/0026 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/2255 , G11C13/0028 , G11C13/004 , G11C13/0069
摘要： A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.
摘要翻译：一种电阻式存储装置，包括具有第一开关单元的列解码器，该第一开关单元包括对应于多条信号线中的每一条布置的至少一对开关，以及第二开关单元，该第二开关单元包括对应于至少第一开关单元的一对开关。第一开关单元的第一对开关包括相同类型的第一开关和第二开关，第二开关单元的第二对开关包括第三开关和第四开关，第三开关和第四开关连接到第一开关一对开关通过穿过第一开关将选择电压提供给第一信号线，并且通过选择性地通过第一开关或第二开关将第一信号线提供禁止电压。

25. 发明授权

US07599222B2 Semiconductor memory device using pipelined-buffer programming and related method 失效
标题翻译：半导体存储器件采用流水线缓冲编程及相关方法
公开(公告)号：US07599222B2
公开(公告)日：2009-10-06
申请号：US11520665
申请日：2006-09-14
申请人： Chi-Weon Yoon , Heung-Soo Lim
发明人： Chi-Weon Yoon , Heung-Soo Lim
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/26 , G11C16/3454 , G11C2216/14
摘要： Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.
摘要翻译：公开了一种半导体存储器件，其可操作流水线缓冲器编程，并且包括包括多个存储器单元的单元阵列，分成多个写单元的写驱动器电路，每个写单元编程存储单元与第一数据，读取放大器电路被划分为与多个写入单元相同数量的读取单元，每个读取单元在程序验证操作期间感测单元阵列的位线，用于选择写入单元之一的选择电路和响应于列地址读取单元和数据输入电路，用于在编程操作期间将所述第一数据提供给所选择的写入单元，并且用于在所述程序验证操作期间从所选择的读取单元接收验证数据。

26. 发明申请

US20080031050A1 FLASH MEMORY DEVICE HAVING A DATA BUFFER AND PROGRAMMING METHOD OF THE SAME 有权
标题翻译：具有数据缓冲器的闪存存储器件及其编程方法
公开(公告)号：US20080031050A1
公开(公告)日：2008-02-07
申请号：US11775872
申请日：2007-07-11
申请人： Chi-Weon Yoon , Heung-Soo Lim
发明人： Chi-Weon Yoon , Heung-Soo Lim
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C16/06
摘要： A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells, the data having sequential data addresses. The write driver programs the data stored in the data buffer into the memory cells during one programming operation. The controller controls operations of the data buffer and the write driver, and performs flexible mapping between addresses of the data buffer and the data addresses based on a first address of the data.
摘要翻译：闪存器件包括具有多个存储器单元的存储单元阵列，数据缓冲器，写入驱动器和控制器。数据缓冲器将要编程的数据存储到存储器单元中，数据具有顺序数据地址。写入驱动器在一个编程操作期间将存储在数据缓冲器中的数据编程到存储器单元中。控制器控制数据缓冲器和写入驱动器的操作，并且基于数据的第一地址在数据缓冲器的地址和数据地址之间执行灵活的映射。

27. 发明申请

US20070150646A1 Semiconductor memory device using pipelined-buffer programming and related method 失效
标题翻译：半导体存储器件采用流水线缓冲编程及相关方法
公开(公告)号：US20070150646A1
公开(公告)日：2007-06-28
申请号：US11520665
申请日：2006-09-14
申请人： Chi-Weon Yoon , Heung-Soo Lim
发明人： Chi-Weon Yoon , Heung-Soo Lim
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C16/26 , G11C16/3454 , G11C2216/14
摘要： Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.
摘要翻译：公开了一种半导体存储器件，其可操作流水线缓冲器编程，并且包括包括多个存储器单元的单元阵列，分成多个写单元的写驱动器电路，每个写单元编程存储单元与第一数据，读取放大器电路被划分为与多个写入单元相同数量的读取单元，每个读取单元在程序验证操作期间感测单元阵列的位线，用于选择写入单元之一的选择电路和响应于列地址读取单元和数据输入电路，用于在编程操作期间将所述第一数据提供给所选择的写入单元，并且用于在所述程序验证操作期间从所选择的读取单元接收验证数据。

28. 发明申请

US20070147136A1 Flash memory device and related erase operation 有权
标题翻译：闪存设备和相关擦除操作
公开(公告)号：US20070147136A1
公开(公告)日：2007-06-28
申请号：US11501070
申请日：2006-08-09
申请人： Chi-Weon Yoon , Heung-Soo Lim
发明人： Chi-Weon Yoon , Heung-Soo Lim
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/3409 , G11C16/345 , G11C16/3477
摘要： An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.
摘要翻译：闪存器件的擦除操作包括基于地址识别包括多个扇区的扇区组，同时对扇区组中的扇区进行预编程，同时擦除扇区组，并同时对扇区进行后编程行业组。

29. 发明授权

US06907078B2 Method for storing compressed MPEG image with low power consumption and frame buffer structure used in the same 失效
标题翻译：用于存储具有低功耗的压缩MPEG图像和帧缓冲结构的方法
公开(公告)号：US06907078B2
公开(公告)日：2005-06-14
申请号：US10055916
申请日：2002-01-28
申请人： Hoi-Jun Yoo , Chi-Weon Yoon
发明人： Hoi-Jun Yoo , Chi-Weon Yoon
IPC分类号： H04N7/24 , G06T9/00 , H04N7/26 , H04N7/50 , H04N7/12
CPC分类号： H04N19/423 , H04N19/61
摘要： Disclosed is a frame buffer structure having a sub-word line way of 9 banks in which a dispersed 9-tile mapping shaped data storing method and a partial activation for the method are possible, the frame buffer structure requiring a low power consumption, and a frame buffer being integrated with a logic to properly correspond to an application region to process an MPEG image signal. A method for storing a compressed MPEG image in the frame buffer, comprises: a first step of dividing an image frame into 8×8 pixels regions; a second step of re-designating the respective divided pixel regions into 9 adjacent blocks regions having a form of 3×3; a third step of mapping the 8×8 pixel regions consisting of the 9 adjacent blocks regions having the form of 3×3 into one column; and a fourth step of dispersion-storing the mapped 9 blocks regions of 8×8 pixel regions in different banks.
摘要翻译：公开了一种帧缓冲结构，其具有9个子区的子字线方式，其中分散的9瓦片映射形状数据存储方法和该方法的部分激活是可能的，需要低功耗的帧缓冲结构，以及帧缓冲器与逻辑集成以适当地对应于应用区域以处理MPEG图像信号。一种用于将压缩的MPEG图像存储在帧缓冲器中的方法，包括：将图像帧划分为8×8个像素区域的第一步骤; 将各个划分的像素区域重新指定为具有3×3形式的9个相邻块区域的第二步骤; 将由具有3×3形式的9个相邻块区域组成的8×8像素区域映射到一列中的第三步骤; 以及在不同的存储体中分散存储8×8像素区域的映射的9个块区域的第四步骤。

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