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21. 发明授权

US6141169A System and method for control of low frequency input levels to an amplifier and compensation of input offsets of the amplifier 失效
标题翻译：用于控制放大器的低频输入电平的系统和方法以及放大器的输入偏移的补偿
公开(公告)号：US6141169A
公开(公告)日：2000-10-31
申请号：US956569
申请日：1997-10-23
申请人： David M. Pietruszynski , Jerrell P. Hein , William G. Bliss , German S. Feyh
发明人： David M. Pietruszynski , Jerrell P. Hein , William G. Bliss , German S. Feyh
IPC分类号： G11B5/00 , G11B5/09 , G11B7/09 , G11B20/10 , H03F1/30 , H03F3/45 , G11B5/02
CPC分类号： H03F3/45748 , G11B20/10009 , H03F1/303 , H03F3/45973 , G11B2005/0013 , G11B5/09 , G11B7/0941 , G11B7/0948
摘要： A system and method for an amplifier control circuit is provided which does not require the use of a large off-chip or on-chip capacitor for achieving a low frequency coupling corner, while still effectively allowing AC coupling the data detection circuit. In addition, the input offset voltage to the amplifier may be compensated and the inherent random low frequency input voltages provided to the amplifier may be controlled or canceled. Further, the amplifier control circuitry includes a freeze capability which allows the control circuitry to halt all updates to the input offset/low frequency control circuit when the voltage input signal is interrupted. In addition low frequency control and offset compensation updates may be performed without causing large output signal glitches so that the integrity of the received signal will not be compromised. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.
摘要翻译：提供一种用于放大器控制电路的系统和方法，其不需要使用大的片外或片上电容器来实现低频耦合角，同时仍然有效地允许AC耦合数据检测电路。此外，可以补偿放大器的输入失调电压，并且可以控制或取消提供给放大器的固有的随机低频输入电压。此外，放大器控制电路包括冻结能力，其允许控制电路在电压输入信号中断时停止对输入偏移/低频控制电路的所有更新。此外，可以执行低频控制和偏移补偿更新，而不会导致大的输出信号毛刺，从而不会损害接收信号的完整性。在优选实施例中，系统和方法可以用于与光盘结合使用的数据检测电路。

22. 发明授权

US07288998B2 Voltage controlled clock synthesizer 有权
标题翻译：电压时钟合成器
公开(公告)号：US07288998B2
公开(公告)日：2007-10-30
申请号：US11270957
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/197 , H03L7/1976 , H03L7/23 , H03L7/235 , H03L2207/50 , H04J3/0688
摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
摘要翻译：电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

23. 发明授权

US07158633B1 Method and apparatus for monitoring subscriber loop interface circuitry power dissipation 有权
标题翻译：监控用户环路接口电路功耗的方法和装置
公开(公告)号：US07158633B1
公开(公告)日：2007-01-02
申请号：US09441380
申请日：1999-11-16
申请人： Jerrell P. Hein
发明人： Jerrell P. Hein
IPC分类号： H04M1/00 , H04M9/00
CPC分类号： H04M19/00
摘要： Subscriber line interface circuitry includes an integrated circuit having sense inputs for a sensed tip signal and a sensed ring signal of a subscriber loop. The integrated circuit generates a subscriber loop linefeed driver control signal in response to the sensed signals. The linefeed driver does not reside with the integrated circuit. A method for monitoring power dissipation of the linefeed driver components includes the step of sampling at least one of the tip and ring signals to determine a line voltage and a line current of a selected linefeed driver component. Instantaneous power dissipation of the linefeed component is estimated and then filtered to generate an estimated junction temperature of the linefeed component. In one embodiment, the linefeed driver includes a tip fuse series-coupled to the tip line and a ring fuse series-coupled to the ring line. Voltages sampled from each side of the series-coupled tip fuse resistor and the series-coupled ring fuse and resistors collectively form the sensed tip signal and sensed ring signal, respectively. This enables using the same sensing circuitry for power monitoring as well as to determine other line conditions such as whether the fuses are blown without the use of separate sensing circuitry dedicated to that purpose. This approach reduces the number of pins on an integrated circuit needed to monitor power dissipation and determine pre-fuse line conditions.
摘要翻译：用户线接口电路包括具有用于感测的尖端信号的感测输入和用户环路的感测振铃信号的集成电路。集成电路响应于感测信号产生用户环路线路馈送驱动器控制信号。换行驱动器不在集成电路中。用于监视换行驱动器部件的功率消耗的方法包括对尖端和振铃信号中的至少一个进行采样以确定所选择的线路馈送驱动器部件的线路电压和线路电流的步骤。估计换行组件的瞬时功率消耗，然后过滤以产生换行组件的估计结温。在一个实施例中，换行驱动器包括串联耦合到尖端线的尖端熔丝和串联耦合到环线的环形熔丝。从串联耦合尖端熔丝电阻器和串联耦合的熔丝和电阻器的每一侧采样的电压分别共同形成感测的尖端信号和感测的环形信号。这使得能够使用相同的感测电路进行功率监测，并且确定其他线路状况，例如熔丝是否被熔断，而不使用专用于该目的的单独的感测电路。这种方法减少了监控功耗所需的集成电路引脚数，并确定了预熔丝线路条件。

24. 发明授权

US06724891B1 Integrated modem and line-isolation circuitry and associated method powering caller ID circuitry with power provided across an isolation barrier 失效
标题翻译：集成的调制解调器和线路隔离电路和相关方法为通过隔离屏障提供电源的呼叫者ID电路供电
公开(公告)号：US06724891B1
公开(公告)日：2004-04-20
申请号：US09603382
申请日：2000-06-26
申请人： Yunteng Huang , George T. Tuttle , Timothy J. Dupuis , Jerrell P. Hein
发明人： Yunteng Huang , George T. Tuttle , Timothy J. Dupuis , Jerrell P. Hein
IPC分类号： H04M1738
CPC分类号： H04L25/4927 , H04L7/033 , H04L25/0266 , H04L27/00
摘要： An improved modem architecture and associated method are disclosed that integrate modem and line-isolation circuitry so as to achieve modem functionality and system-side isolation functionality on a single integrated circuit. The combined modem and line isolation system includes a line-side line-isolation integrated circuit which contains caller ID circuitry. The caller ID circuitry includes a caller ID analog to digital converter for processing caller ID data. The caller ID analog to digital converter may be powered by a power supply generated from power provided across a capacitive isolation barrier. The caller ID circuitry may be coupled to the ringer inputs of the line-side line-isolation integrated circuit. The ringer inputs may be capacitively coupled to the phone line.
摘要翻译：公开了一种改进的调制解调器架构和相关联的方法，其集成了调制解调器和线路隔离电路，以便在单个集成电路上实现调制解调器功能和系统侧隔离功能。组合的调制解调器和线路隔离系统包括线路侧线路隔离集成电路，其包含呼叫者ID电路。呼叫者ID电路包括用于处理呼叫者ID数据的来电显示模拟数字转换器。呼叫者模拟到数字转换器可以由通过电容隔离屏障提供的电力产生的电源供电。呼叫者ID电路可以耦合到线路侧线路隔离集成电路的振铃器输入端。振铃器输入可以电容耦合到电话线路。

25. 发明授权

US6111712A Method to improve the jitter of high frequency phase locked loops used in read channels 失效
标题翻译：改善读通道中使用的高频锁相环的抖动的方法
公开(公告)号：US6111712A
公开(公告)日：2000-08-29
申请号：US36608
申请日：1998-03-06
申请人： G. Diwakar Vishakhadatta , Jerrell P. Hein
发明人： G. Diwakar Vishakhadatta , Jerrell P. Hein
IPC分类号： G11B19/247 , G11B20/10 , G11B20/14 , H03L7/089 , H03L7/199 , H03L7/23 , G11B5/09
CPC分类号： H03L7/199 , G11B19/247 , G11B20/10009 , H03L7/23 , G11B20/1403 , H03L7/0891
摘要： A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.
摘要翻译：提供了一种提高读/写通道电路中使用的高频合成器的抖动性能的系统和方法。频率合成器由级联方式布置的多个锁相环实现，以增加级联环路在合成器的给定频率分辨率下工作的更新速率。级联或分级锁相环可用于为读/写通道电路产生读，写和伺服时钟。级联锁相环也可以被布置为使得一个或多个级被共享以产生读，写或伺服时钟。

26. 发明授权

US6028727A Method and system to improve single synthesizer setting times for small frequency steps in read channel circuits 失效
标题翻译：提高读通道电路中小频率步长单合成器设定时间的方法和系统
公开(公告)号：US6028727A
公开(公告)日：2000-02-22
申请号：US924190
申请日：1997-09-05
申请人： G. Diwakar Vishakhadatta , Jerrell P. Hein
发明人： G. Diwakar Vishakhadatta , Jerrell P. Hein
IPC分类号： G11B20/10 , G11B20/14 , H03L7/089 , H03L7/099 , H03L7/10 , H03L7/187 , H03L7/199 , G11B5/09
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/1403 , H03L7/0891 , H03L7/099 , H03L7/10 , H03L7/187 , H03L7/199
摘要： A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times. In one embodiment the oscillator is a current controlled oscillator and the control current to the oscillator is modified based on whether the data frequency synthesizer is utilized for a read operation or a write operation.
摘要翻译：公开了一种系统和方法，其中当需要合成器快速切换频率时，提供电路以改善在读/写通道应用中使用的合成器的稳定性能。这在使用全数字PLL执行时钟恢复的读通道应用中非常有用。使用数字定时恢复方案，其中一个数据频率合成器提供写入和读取频率。读取频率设置为高于写入频率，以便在从存储介质读取数据时允许过采样。当从写入到读取频率变化时，频率合成器快速地定位到新的频率。频率合成器包括利用可控振荡器的锁相环。改变锁相环除数以获得所需的频率变化。向可控振荡器的输入信号也被改变以获得快速的建立时间。在一个实施例中，振荡器是电流控制振荡器，并且基于数据频率合成器是否用于读取操作或写入操作来修改到振荡器的控制电流。

27. 发明授权

US5986830A Read/write channel write precompensation system and method using one or more delay clocks 失效
标题翻译：读/写通道写入预补偿系统和方法使用一个或多个延迟时钟
公开(公告)号：US5986830A
公开(公告)日：1999-11-16
申请号：US902832
申请日：1997-07-30
申请人： Jerrell P. Hein
发明人： Jerrell P. Hein
IPC分类号： G11B5/012 , G11B5/035 , G11B20/10 , G11B20/14 , G11B5/09
CPC分类号： G11B20/1403 , G11B20/10009 , G11B5/035 , G11B5/012
摘要： An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.
摘要翻译：提供了一种用于读/写通道电路和系统的改进的预预补偿电路。提供了多个数据输入信号，每个数据输入信号由不同的时钟计时。然后数据输入信号被复用。可以使用两个，三个或更多个数据时钟延迟来提供两个，三个或更多个数据延迟以实现写入预补偿。在多路复用器可能改变状态之前，信号的仅一个边缘需要通过多路复用器。延迟量可能是用户可编程的。

28. 发明授权

US07825708B2 Dual loop architecture useful for a programmable clock source and clock multiplier applications 有权
标题翻译：双循环架构可用于可编程时钟源和时钟乘法器应用
公开(公告)号：US07825708B2
公开(公告)日：2010-11-02
申请号：US12249457
申请日：2008-10-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein
IPC分类号： H03L7/06
CPC分类号： H03L1/022 , H03L1/026 , H03L7/095 , H03L7/0992 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.
摘要翻译：第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

29. 发明授权

US07486787B2 Subscriber line interface circuitry with common base audio isolation stage 有权
标题翻译：用户线接口电路，具有公共基本音频隔离级
公开(公告)号：US07486787B2
公开(公告)日：2009-02-03
申请号：US11278405
申请日：2006-03-31
申请人： Jerrell P. Hein , Marius Goldenberg
发明人： Jerrell P. Hein , Marius Goldenberg
IPC分类号： H04M9/00
CPC分类号： H04M3/005
摘要： Methods and apparatus for coupling outgoing analog audio signals to a subscriber line are described. One method includes the step of receiving the outgoing audio signal. The outgoing audio signal is coupled to the subscriber line through a plurality of transistors coupled in a common base configuration. In one embodiment, linefeed driver control signals for controlling battery feed to the subscriber line are received on the same signal lines as the outgoing audio signal. A subscriber line interface circuit apparatus includes a first circuit for coupling a received outgoing audio signal to a subscriber line. The first circuit couples the received outgoing audio signal to the subscriber line through a common base isolation stage. In various embodiments, the common base isolation stage comprises a plurality of bipolar junction transistors coupled in a common base configuration or a plurality of field effect transistors coupled in a common gate configuration.
摘要翻译：描述了将出口模拟音频信号耦合到用户线的方法和装置。一种方法包括接收输出音频信号的步骤。输出音频信号通过以公共基本配置耦合的多个晶体管耦合到用户线路。在一个实施例中，用于控制到用户线的电池馈送的换行驱动器控制信号在与输出音频信号相同的信号线上被接收。用户线接口电路装置包括用于将接收到的输出音频信号耦合到用户线路的第一电路。第一电路通过公共基本隔离级将接收到的输出音频信号耦合到用户线路。在各种实施例中，公共基极隔离级包括以公共基极配置耦合的多个双极结型晶体管或以公共栅极配置耦合的多个场效应晶体管。

30. 发明授权

US07450712B1 Low voltage sensing and control of battery referenced transistors in subscriber loop applications 有权
标题翻译：用户环路应用中电池参考晶体管的低电压感测和控制
公开(公告)号：US07450712B1
公开(公告)日：2008-11-11
申请号：US09693652
申请日：2000-10-21
申请人： Jerrell P. Hein , Marius Goldenberg
发明人： Jerrell P. Hein , Marius Goldenberg
IPC分类号： H04M1/00 , H04M9/00
CPC分类号： H04M19/005
摘要： A method includes the step of providing subscriber loop pull-down circuitry operating in a first voltage domain. The subscriber loop pull-down circuitry decreases at least one of a tip and a ring line current in response to a corresponding pull-down control signal. The method further includes the step of providing control circuitry operating in a second voltage domain, wherein the first and second voltage domains are substantially distinct. The control circuitry varies the pull-down control signal to decrease a selected one of the tip and ring line currents in response to a sensed current corresponding to an associated one of a tip pull-down current and a ring pull-down current. A subscriber line interface circuit apparatus includes pull-down circuitry operating in a first voltage domain. The pull-down circuitry varies line currents of the tip and ring lines in response to a pull-down control signal provided by control circuitry operating in a second voltage domain. The first and second voltage domains are substantially distinct. A control isolation stage is coupled to provide the pull-down control signals from the control circuitry to the pull-down circuitry. A feedback isolation stage provides feedback signals from the pull-down circuitry to the control circuitry. The feedback signals represent sensed pull-down currents associated with the tip and ring lines. The control circuitry provides the pull-down control signals for the tip and ring lines in response to the sensed pull-down currents.
摘要翻译：一种方法包括提供在第一电压域中操作的用户环路下拉电路的步骤。响应于相应的下拉控制信号，用户环路下拉电路减少尖端和环线电流中的至少一个。该方法还包括提供在第二电压域中操作的控制电路的步骤，其中第一和第二电压域基本不同。响应于对应于尖端下拉电流和环下拉电流中相关联的一个的感测电流，控制电路改变下拉控制信号以减小尖端和环形线电流中选择的一个。用户线接口电路装置包括在第一电压域中操作的下拉电路。下拉电路响应由在第二电压域中操作的控制电路提供的下拉控制信号，改变尖端和环形线路的线路电流。第一和第二电压域基本不同。耦合控制隔离级以提供从控制电路到下拉电路的下拉控制信号。反馈隔离级提供从下拉电路到控制电路的反馈信号。反馈信号表示与尖端和环线相关联的感测下拉电流。响应感测的下拉电流，控制电路为尖端和环线提供下拉控制信号。

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