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21. 发明申请

US20060222002A1 Configurable ports for a host Ethernet adapter 失效
标题翻译：适用于主机以太网适配器的可配置端口
公开(公告)号：US20060222002A1
公开(公告)日：2006-10-05
申请号：US11097652
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
IPC分类号： H04J3/22 , H04J3/16
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

22. 发明申请

US20060221969A1 System and method for computing a blind checksum in a host ethernet adapter (HEA) 失效
公开(公告)号：US20060221969A1
公开(公告)日：2006-10-05
申请号：US11097430
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04L12/28
CPC分类号： H04L69/16 , H04L69/161
摘要： A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.

23. 发明申请

US20060221961A1 Network communications for operating system partitions 有权
标题翻译：操作系统分区的网络通信
公开(公告)号：US20060221961A1
公开(公告)日：2006-10-05
申请号：US11097051
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L29/06 , H04L49/90 , H04L69/32
摘要： Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.
摘要翻译：提供操作系统分区与计算机网络之间的通信。一方面，一种用于在多个操作系统分区之间分配网络通信的装置包括允许网络和计算机系统之间的通信的物理端口以及与物理端口相关联的逻辑端口，其中每个逻辑端口与操作系统之一相关联分区。每个逻辑端口实现物理端口与相关联的操作系统分区之间的通信，并允许系统的网络资源的可配置性。其他方面包括用于逻辑和物理端口的逻辑交换机，以及每个连接和每个逻辑端口的分组队列。

24. 发明申请

US20060221952A1 System and method for parsing, filtering, and computing the checksum in a host ethernet adapter (HEA) 有权
标题翻译：在主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法
公开(公告)号：US20060221952A1
公开(公告)日：2006-10-05
申请号：US11096365
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
IPC分类号： H04J3/24 , H04L12/56 , H04L12/28
CPC分类号： H04L1/0052 , H04L1/0061
摘要： A system and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) that is coupled to a host. The method includes receiving a part of a frame, wherein a plurality of parts of a frame constitute a entire frame. Next, parse the part of a frame before receiving the entire frame. The HEA computes a checksum of the part of a frame. The HEA filters the part of a frame based on a logical, port-specific policy and transmits the checksum to the host.
摘要翻译：用于在耦合到主机的主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法。该方法包括接收帧的一部分，其中帧的多个部分构成整个帧。接下来，在接收整个帧之前解析帧的一部分。 HEA计算帧的一部分的校验和。 HEA基于逻辑，端口特定策略过滤帧的一部分，并将校验和传送到主机。

25. 发明申请

US20060206684A1 Systems and methods for multi-frame control blocks 有权
公开(公告)号：US20060206684A1
公开(公告)日：2006-09-14
申请号：US11076218
申请日：2005-03-09
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
IPC分类号： G06F12/00 , G06F9/34
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

26. 发明申请

US20060200615A1 Systems and methods for adaptively mapping an instruction cache 失效
标题翻译：用于自适应地映射指令高速缓存的系统和方法
公开(公告)号：US20060200615A1
公开(公告)日：2006-09-07
申请号：US11070758
申请日：2005-03-02
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Harm Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Harm Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Verplanken , Colin Verrilli
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.
摘要翻译：公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。基于观察结果，可以确定最小化碰撞的最佳映射。

27. 发明申请

US20060039376A1 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US20060039376A1
公开(公告)日：2006-02-23
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

28. 发明申请

US20050259659A1 Method for prevention of out-of-order delivery of data 失效
标题翻译：防止数据乱序传送的方法
公开(公告)号：US20050259659A1
公开(公告)日：2005-11-24
申请号：US10850296
申请日：2004-05-20
申请人： Claude Basso , Jean Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/56 , H04L29/06
CPC分类号： H04L69/166 , H04L29/06 , H04L69/16
摘要： A method for sequencing delivery of information packets from a router having several processing elements to a receiving processing installation, wherein delivery of the packets must be completed in the order the packets arrive at the router. A linked list of packets is formed in the order they are received at the router, and each packet fragmented into successive fragments. Each fragment is processed at the router. The last fragment of each packet in each linked list is labeled with the sequence in which the packet was received, and enqueued in the order labeled for each last fragment on each linked list. Each fragment of each packet is delivered as processed, except the last fragment of each packet on its linked list to the receiving processor installation, and thereafter, transmitting the final fragment of each packet after processing only if that fragment is at the head of the queue.
摘要翻译：一种用于将信息分组从具有多个处理元件的路由器传送到接收处理设备的方法，其中分组的传送必须按分组到达路由器的顺序完成。分组的链表以它们在路由器处接收的顺序形成，并且每个分组被分段成连续的片段。每个片段在路由器处理。每个链表中每个数据包的最后一个片段都标有接收数据包的顺序，并按照每个链表上每个最后一个片段标记的顺序排队。每个分组的每个片段被处理，除了其链接列表上的每个分组的最后片段到接收处理器安装，然后在处理之后仅在该片段位于队列的头部时发送每个分组的最后片段。

29. 发明申请

US20120198213A1 PACKET HANDLER INCLUDING PLURALITY OF PARALLEL ACTION MACHINES 审中-公开
标题翻译：包装处理器，包括平行动作机械的多样性
公开(公告)号：US20120198213A1
公开(公告)日：2012-08-02
申请号：US13017949
申请日：2011-01-31
申请人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
发明人： Francois Abel , Jean Calvignac , Christoph Hagleitner , Fabrice Verplanken
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3016 , G06F9/3889
摘要： A packet handler for a packet processing system includes a plurality of parallel action machines, each of the plurality of parallel action machines being configured to perform a respective packet processing function; and a plurality of action machine input registers, wherein each of the plurality of parallel action machines is associated with one or more of the plurality of action machine input registers, and wherein an action machine of the plurality of parallel action machines is automatically triggered to perform its respective packet processing function in the event that data sufficient to perform the actions machine's respective packet processing function is written into the action machine's one or more respective action machine input registers.
摘要翻译：用于分组处理系统的分组处理器包括多个并行动作机器，所述多个并行动作机器中的每一个被配置为执行相应的分组处理功能; 以及多个动作机械输入寄存器，其中，所述多个并行动作机器中的每一个与所述多个动作机械输入寄存器中的一个或多个相关联，并且其中，所述多个并行动作机器的动作机器被自动触发以执行在足以执行动作机器相应的分组处理功能的数据被写入动作机器的一个或多个相应动作机器输入寄存器的情况下，其各自的分组处理功能。

30. 发明申请

US20060251120A1 Host ethernet adapter for networking offload in server environment 失效
标题翻译：主机以太网适配器，用于在服务器环境中进行网络卸载
公开(公告)号：US20060251120A1
公开(公告)日：2006-11-09
申请号：US11097608
申请日：2005-04-01
申请人： Ravi Arimilli , Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Satya Sharma , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Ravi Arimilli , Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Satya Sharma , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04J3/16
CPC分类号： H04L12/413 , H04L12/40032 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/324
摘要： An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.
摘要翻译：公开了一种以太网适配器。以太网适配器包括多个层，用于允许适配器从处理器接收和发送分组。多个层包括多路分解机制以允许处理器的划分。主机以太网适配器（HEA）是集成的以太网适配器，为以太网和TCP加速提供了新的方法。一组TCP / IP加速功能已经在工具包方法中引入：服务器TCP / IP堆栈在需要时使用这些加速器。服务器和网络接口控制器之间的接口通过绕过PCI总线进行了简化。 HEA支持网络虚拟化。 HEA可以由多个操作系统共享，提供基本的隔离和保护，而不会影响其性能。

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