专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5563746A Real time media defect scanning in a sampled amplitude read channel 失效
标题翻译：采样振幅读通道中的实时介质缺陷扫描
公开(公告)号：US5563746A
公开(公告)日：1996-10-08
申请号：US341234
申请日：1994-11-17
申请人： William G. Bliss
发明人： William G. Bliss
IPC分类号： G11B5/09 , G11B20/18 , G11B27/36 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10037 , G11B20/1816 , G11B20/182 , G11B27/36 , G11B5/09 , G11B2020/1476
摘要： A real time defect scanning system integrated into a sampled amplitude read channel for detecting defects in a magnetic storage medium using a discrete time filter having an impulse response substantially matched to an error signature in a read back signal caused by a defect in the medium. The scanning system operates by writing a predetermined bit sequence to the storage device and detecting medium defects upon read back. In a sinusoidal read signal mode, a discrete time notch filter removes the fundamental frequency so that any remaining sidebands indicate a media defect. The discrete time defect filter enhances the signal so that a defect can be detected with a discrete time energy detector. The impulse responses of the notch filter and defect detection filter are programmable in order to adapt the defect scanning system to a particular disk drive, data density, or magnetic media.
摘要翻译：一种集成到采样幅度读取通道中的实时缺陷扫描系统，用于使用离散时间滤波器来检测磁存储介质中的缺陷，所述离散时间滤波器具有与由介质中的缺陷引起的回读信号中的错误签名基本匹配的脉冲响应。扫描系统通过将预定的比特序列写入存储装置并在读回时检测介质缺陷来操作。在正弦读信号模式中，离散时间陷波滤波器去除基频，使得任何剩余边带指示介质缺陷。离散时间缺陷滤波器增强了信号，从而可以用离散的时间能量检测器检测到缺陷。陷波滤波器和缺陷检测滤波器的脉冲响应是可编程的，以便将缺陷扫描系统适应于特定的磁盘驱动器，数据密度或磁介质。

22. 发明授权

US07904795B2 Iterative decoder with stopping criterion generated from error location polynomial 有权
标题翻译：具有从错误位置多项式生成的停止标准的迭代解码器
公开(公告)号：US07904795B2
公开(公告)日：2011-03-08
申请号：US12397237
申请日：2009-03-03
申请人： Yu Liao , William G. Bliss , Engling Yeo
发明人： Yu Liao , William G. Bliss , Engling Yeo
IPC分类号： H03M13/00
CPC分类号： H03M13/3753 , H03M13/1525 , H03M13/2906 , H03M13/2936
摘要： A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.
摘要翻译：用于由编码消息（例如由turbo编码器编码的编码消息）进行纠错的解码器，由于改进的停止标准而具有减少的迭代。解码器包括错误校正循环，其循环地处理在通过通信信道传送之前被编码的消息。误差校正循环，例如利用Reed-Solomon解码器，在每个迭代过程中产生误差位置多项式。解码器中的停止机制允许基于错误位置多项式的消息解码的附加迭代，例如通过获得错误位置多项式的程度并将其与阈值进行比较。在一个示例中，阈值是由解码器中实现的Reed-Solomon码可校正的符号错误的最大数量。当停止标准（或多项式度）大于由里德 - 所罗门码可校正的符号错误的最大数量时，停止机制允许额外的迭代。

23. 发明授权

US07053801B2 High rate coding for media noise 有权
标题翻译：高速编码媒体噪声
公开(公告)号：US07053801B2
公开(公告)日：2006-05-30
申请号：US10869843
申请日：2004-06-18
申请人： William G. Bliss , Andrei Vityaev , Razmik Karabed
发明人： William G. Bliss , Andrei Vityaev , Razmik Karabed
IPC分类号： H03M7/00
CPC分类号： G11B20/1426 , G11B20/10009 , G11B20/1833 , G11B2020/1446 , H03M5/145 , H03M13/093
摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.
摘要翻译：一种装置具有转换电路，预编码器电路和选择电路。转换电路转换用户数据b 1，b 2，b 3 3。。。对于编码序列c 0，c 1，c 2，...，。。 c 。选择电路在编码序列c 0 0，c 1，c 2 2中选择c <0> 0 。。。使得预编码器电路的输出具有小于转换的最大数量q。转换电路可以包括用于转换用户数据b 1，b 2，b 3 3的编码器电路。。。 c 到序列c 1，c 2。。。以及向序列c 1，c 2 2加上c 0的转换最小化电路。。。 c 。该装置可以具有电路，用于将至少一个额外的位（其可以是奇偶校验位）添加到编码序列c 0，c 1，c 2 。。。 c 。

24. 发明授权

US06809894B2 Method and apparatus for handling end of data processing in a data storage device 有权
标题翻译：一种处理数据存储装置中的数据处理结束的方法和装置
公开(公告)号：US06809894B2
公开(公告)日：2004-10-26
申请号：US09896135
申请日：2001-06-29
申请人： William G. Bliss , Razmik Karabed , James W. Rae , Heiner Stockmanns , Kaichi Zhang
发明人： William G. Bliss , Razmik Karabed , James W. Rae , Heiner Stockmanns , Kaichi Zhang
IPC分类号： G11B509
CPC分类号： G11B20/1217 , G11B20/10009 , G11B2220/2516
摘要： A method and apparatus for handling end of data processing in a data storage device. The method includes receiving a plurality of user data bits at a write channel. The method further includes appending primary padding bits to user data bits if the plurality of user data bits is less than a multiple of an input block length of an encoder in the write channel and encoding the plurality of user data bits and any primary padding bits into a plurality of encoded data bytes. Additionally, the method includes appending an end of data marker to an end of the plurality of encoded data bytes, wherein the end of data marker has a length of no more than one byte, and writing the plurality of encoded data bytes and the end of data marker to the data store.
摘要翻译：一种处理数据存储装置中的数据处理结束的方法和装置。该方法包括在写入通道处接收多个用户数据位。该方法还包括：如果多个用户数据位小于写通道中编码器的输入块长度的倍数，并将多个用户数据位和任何主填充位编码为多个，则将主填充位附加到用户数据位多个编码数据字节。此外，该方法包括将数据标记的结尾附加到多个编码数据字节的末尾，其中数据标记的结尾具有不超过一个字节的长度，并写入多个编码数据字节和结束数据标记到数据存储。

25. 发明授权

US06788482B2 Method and apparatus for Viterbi detector state metric re-normalization 有权
标题翻译：维特比检测器状态度量重新归一化的方法和装置
公开(公告)号：US06788482B2
公开(公告)日：2004-09-07
申请号：US09896134
申请日：2001-06-29
申请人： William G. Bliss , Razmik Karabed , James W. Rae , Heiner Stockmanns
发明人： William G. Bliss , Razmik Karabed , James W. Rae , Heiner Stockmanns
IPC分类号： G11B509
CPC分类号： H03M13/6343 , G11B20/10009 , H03M13/3961 , H03M13/4107 , H03M13/6502 , H03M13/6583
摘要： A method and apparatus for Viterbi detector state metric re-normalization. The method includes fabricating a Viterbi detector (138) having a predetermined number of states, wherein the Viterbi detector (138) stores a state metric value and a branch metric value for each state, and wherein the Viterbi detector (138) implements a trellis diagram. The method includes constructing a Viterbi detector (138) which can support a state metric value having g+h′ number of bits. The number of bits needed to represent the branch metric value is represented by (g) and the additional number of bits needed to represent the state metric value is represented by (h′). The additional number of bits (h′) is less than the additional number of bits (h) determined using the following inequality: 2h−1−h≧K−1, wherein K represent the constraint length of the trellis diagram.
摘要翻译：一种用于维特比检测器状态度量重新归一化的方法和装置。该方法包括制造具有预定数量状态的维特比检测器（138），其中维特比检测器（138）存储每个状态的状态度量值和分支度量值，并且其中维特比检测器（138）实现格状图。该方法包括构造可支持具有g + h'比特数的状态度量值的维特比检测器（138）。表示分支量度值所需的位数由（g）表示，表示状态量度值所需的附加位数由（h'）表示。附加位数（h'）小于使用以下不等式确定的附加位数（h）：2 -h> = K-1，其中K表示网格图的约束长度。

26. 发明授权

US06771442B2 Off-track interference emulator 有权
标题翻译：离线干扰仿真器
公开(公告)号：US06771442B2
公开(公告)日：2004-08-03
申请号：US09896885
申请日：2001-06-29
申请人： William G. Bliss , James W. Rae
发明人： William G. Bliss , James W. Rae
IPC分类号： G11B509
CPC分类号： G11B20/10481 , G11B5/012 , G11B5/09 , G11B20/10009 , G11B20/1816 , G11B27/36 , G11B2220/20
摘要： An apparatus and method for adding errors to magnetic data and then detecting the errors is revealed. The method includes providing a magnetic recording channel, reading and digitizing a stored signal, introducing an error signal that emulates off-track interference, adding the error to the digitized signal, and determining an error rate. The apparatus includes a magnetic recording channel having a linear feedback shift register to generate a pseudo-random binary sequence, circuitry to convert the sequence into an error signal, and a Viterbi detector to quantify an error rate.
摘要翻译：揭示了一种用于向磁数据添加错误然后检测错误的装置和方法。该方法包括提供磁记录通道，读取和数字化存储的信号，引入模拟偏离轨道干扰的误差信号，将误差加到数字化信号上，并确定错误率。该装置包括具有线性反馈移位寄存器以产生伪随机二进制序列的磁记录通道，将该序列转换为误差信号的电路以及量化误码率的维特比检测器。

27. 发明授权

US06753797B2 Multiproperty 16/17 trellis code 有权
标题翻译：多重16/17格码
公开(公告)号：US06753797B2
公开(公告)日：2004-06-22
申请号：US10253993
申请日：2002-09-25
申请人： William G. Bliss , Razmik Karabed
发明人： William G. Bliss , Razmik Karabed
IPC分类号： H03M700
CPC分类号： G11B20/1426 , G11B2020/1446 , H03M5/145
摘要： A coding system that in a first embodiment is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords has an 8-bit first half and a 9-bit second half, wherein the first half has at least 3 or more ones, and wherein the second half comprises at least 3 or more ones. The first half and second half of the codewords each have odd-coordinate bits and even-coordinate bits, at least one odd-coordinate bit of each half has a value of one, and at least one even-coordinate bit of each half has a value of one. In a second embodiment, the coding system is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords have an 11-bit first half and a 6-bit second half, wherein the first half comprises at least 3 or more ones, and wherein the second half has at least 2 or more ones. The last half of the codewords have odd-coordinate bits and even-coordinate bits, and wherein at least one odd-coordinate bit of the last half has a value of one, and at least one even-coordinate bit of the last half has a value of one.
摘要翻译：在第一实施例中的编码系统能够将16位输入字编码成偶校验17位码字，其中码字具有至少7个码字，其中码字具有8位前半位和9位第二位一半，其中所述第一半具有至少3个或更多个，并且其中所述第二半包括至少3个或更多个。码字的前半部分和后半部分均具有奇数坐标位和偶坐标位，每一半的至少一个奇数坐标位具有值1，并且每一半的至少一个偶坐标位具有价值一。在第二实施例中，编码系统能够将16位输入字编码为偶校验17位码字，其中码字具有至少7个码字，其中码字具有11位前半位和6位第二位一半，其中所述前半部包括至少3个以上，并且其中所述第二半具有至少2个以上。码字的最后一半具有奇数坐标位和偶坐标位，并且其中最后一半的至少一个奇数坐标位具有值1，并且最后一半的至少一个偶坐标位具有价值一。

28. 发明授权

US06731443B2 Total error multiplier for optimizing read/write channel 有权
标题翻译：用于优化读/写通道的总误差乘数
公开(公告)号：US06731443B2
公开(公告)日：2004-05-04
申请号：US09896640
申请日：2001-06-29
申请人： William G. Bliss , James W. Rae
发明人： William G. Bliss , James W. Rae
IPC分类号： G11B509
CPC分类号： G11B20/1816 , G11B20/10009 , G11B20/22
摘要： A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood (“PRML”) read/write channel is disclosed. A channel margining circuit that is configured to carry out an embodiment for a method of optimizing the bit error rates of a read/write channel is described. The margining circuit derives an interference signal to stress a read/write channel for optimizing the bit error rate. The signal is derived from bit errors inherent with the read/write channel. The circuit reduces the time to optimize the channel by providing an amplified interference signal that increases a bit error rate during optimization.
摘要翻译：公开了一种用于优化部分响应，最大似然（“PRML”）读/写通道的误码率的方法和装置。描述了被配置为执行用于优化读/写通道的误码率的方法的实施例的信道余量电路。边缘电路导出干扰信号，以压缩读/写通道，以优化误码率。该信号来自读/写通道固有的位错误。该电路通过提供在优化期间增加误码率的放大干扰信号来减少对信道优化的时间。

29. 发明授权

US06661590B2 Efficient analog front end for a read/write channel of a hard disk drive running from a highly regulated power supply 有权
公开(公告)号：US06661590B2
公开(公告)日：2003-12-09
申请号：US09865860
申请日：2001-05-25
申请人： Sasan Cyrusian , Stephen J. Franck , Sriharsha Annadore , Elmar Bach , Siegfried Hart , Thomas Blon , William G. Bliss , James Wilson Rae , Michael Ruegg , Ulrich Huewels , Fritz Mistlberger
发明人： Sasan Cyrusian , Stephen J. Franck , Sriharsha Annadore , Elmar Bach , Siegfried Hart , Thomas Blon , William G. Bliss , James Wilson Rae , Michael Ruegg , Ulrich Huewels , Fritz Mistlberger
IPC分类号： G11B509
CPC分类号： G11B5/02 , G11B5/012 , G11B20/10009
摘要： A method and apparatus for running an analog portion (162) of a read/write channel (108) from a highly regulated power supply (260). The apparatus includes an analog portion (162), a clock synthesizer (154), and a highly regulated power supply (260) connected to the analog portion (162) and the clock synthesizer (154). The analog portion (162) and the clock synthesizer (154) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply (260) supplies power that is within the first voltage range to the analog portion (162) and the clock synthesizer (154). The method includes generating power that is within the first voltage range using the highly regulated power supply (260), and supplying the power to the analog portion (162) and the clock synthesizer (154).

30. 发明授权

US06449110B1 Optimizing operation of a disk storage system by increasing the gain of a non-linear transducer and correcting the non-linear distortions using a non-linear correction circuit 失效
标题翻译：通过增加非线性传感器的增益并使用非线性校正电路校正非线性失真来优化磁盘存储系统的操作
公开(公告)号：US06449110B1
公开(公告)日：2002-09-10
申请号：US09244082
申请日：1999-02-03
申请人： Ronald D. DeGroat , William G. Bliss
发明人： Ronald D. DeGroat , William G. Bliss
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10009 , G11B20/10037
摘要： A sampled amplitude read channel is disclosed for magnetic disk storage systems utilizing a read head exhibiting a non-linear response such as a magneto-resistive (MR) read head. A sensor of the read head is adjusted to operate in a region of its response that provides optimum gain even though it may be a region of higher non-linearity. To compensate for the non-linearity introduced into the read signal, the read channel further comprises an adaptive non-linear correction circuit that is adaptively tuned by a least-mean-square (LMS) adaptation circuit. The analog read signal is sampled and the discrete time samples equalized into a desired partial response prior to sequence detection. The non-linear correction circuit is inserted into the read path prior to the sequence detector in order to attenuate the non-linear distortions that would otherwise degrade the performance of the sequence detector. A channel quality circuit integrated into the read channel measures and accumulates a predetermined error metric, such as a squared sample error or a bit error, that is used to optimize the adjustment of the sensor in the read head. By iteratively adjusting the sensor and adaptively tuning the non-linear correction circuit, an optimum sensor setting that minimizes the accumulated error metric is determined, saved, and then used as the operating setting during normal operation of the magnetic disk storage system.
摘要翻译：公开了采用磁阻（MR）读头的非线性响应的读头的磁盘存储系统的采样振幅读通道。读头的传感器被调整以在其响应的区域中操作，其提供最佳增益，即使其可以是较高非线性的区域。为了补偿引入读信号的非线性，读通道还包括由最小均方（LMS）适配电路自适应调谐的自适应非线性校正电路。模拟读取信号被采样，并且离散时间样本在序列检测之前被均衡为期望的部分响应。非线性校正电路在序列检测器之前插入到读取路径中，以便衰减否则会降低序列检测器的性能的非线性失真。集成到读通道中的通道质量电路测量并累积预定误差度量，例如用于优化读头中的传感器的调整的采样误差或位错误。通过迭代地调整传感器并自适应地调谐非线性校正电路，确定，保存最小化累积误差度量的最佳传感器设置，然后在磁盘存储系统的正常操作期间用作操作设置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式