专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07488627B1 Thyristor-based memory and its method of operation 失效
标题翻译：基于晶闸管的存储器及其操作方法
公开(公告)号：US07488627B1
公开(公告)日：2009-02-10
申请号：US11487548
申请日：2006-07-15
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L21/332
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
摘要翻译：基于晶闸管的存储器可以包括通过存取晶体管可访问的晶闸管。可以将温度依赖偏压施加到电容耦合到晶闸管的基极区域的支撑衬底和电极中的至少一个。自适应偏置的电压电平可以相对于温度而变化，并且可以根据偏置的变化影响和/或补偿晶闸管的固有双极增益，并且可以在一定范围的工作温度下增强其性能和/或可靠性。在特定实施例中，晶闸管可以形成在SOI衬底的硅层中，并且耦合到SOI结构的支撑衬底的自适应偏置。

22. 发明授权

US07894256B1 Thyristor based memory cell 失效
标题翻译：基于晶闸管的存储单元
公开(公告)号：US07894256B1
公开(公告)日：2011-02-22
申请号：US11881159
申请日：2007-07-25
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： G11C11/39
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
摘要翻译：新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。可以在体硅晶片上制造包含这些存储单元的存储器阵列。存储单元包含晶闸管体和栅极。晶闸管体具有两个端部区域和两个基极区域，并且它设置在阱的顶部。存储单元位于两个隔离区之间，并且隔离区延伸到阱的下方。第一端区连接到字线，位线和第三线之一。第二端区连接到字线，位线和第三线中的另一端。门连接到字线，位线和第三行的剩余部分。

23. 发明授权

US07894255B1 Thyristor based memory cell 失效
标题翻译：基于晶闸管的存储单元
公开(公告)号：US07894255B1
公开(公告)日：2011-02-22
申请号：US11881049
申请日：2007-07-25
申请人： Farid Nemati , Scott Robins , Kevin J. Yang
发明人： Farid Nemati , Scott Robins , Kevin J. Yang
IPC分类号： G11C11/34
CPC分类号： G11C11/39 , H01L27/1027 , H01L29/66393 , H01L29/7436
摘要： A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.
摘要翻译：新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。可以在体硅晶片上制造包含这些存储单元的存储器阵列。每个存储单元通过浅沟槽隔离区与其它存储单元分离。存储单元包括可控硅体和栅极。晶闸管体具有两个端部区域和两个基极区域。栅极定位在一个基极区域的至少一部分上并与另一个基极区域偏移绝缘。第一端区连接到字线，位线和第三线之一。第二端区连接到字线，位线和第三线中的另一端。门连接到字线，位线和第三行的剩余部分。

24. 发明授权

US07078739B1 Thyristor-based memory and its method of operation 失效
公开(公告)号：US07078739B1
公开(公告)日：2006-07-18
申请号：US10741539
申请日：2003-12-19
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

25. 发明授权

US08576649B1 Sense amplifiers and operations thereof 失效
标题翻译：感应放大器及其操作
公开(公告)号：US08576649B1
公开(公告)日：2013-11-05
申请号：US13172017
申请日：2011-06-29
申请人： Farid Nemati
发明人： Farid Nemati
IPC分类号： G11C7/00
CPC分类号： G11C11/39 , G11C7/065 , G11C11/406
摘要： Sense amplifiers and operations thereof are described. More particularly, embodiments of integrated circuit having a sense amplifier coupled to a first bitline and a second bitline of a memory array are described. The sense amplifier generally includes: a latch circuit and a group select input/output circuit, as well as read, reference voltage, and precharge circuitry. Further described is an embodiment of a method for a refresh operation. First data states of a group of memory cells of an array are read and written back as second data states without changing voltages at sense nodes of the latch circuits from the reading, where the second data states are an inverse of the first data states.
摘要翻译：描述了检测放大器及其操作。更具体地，描述了具有耦合到存储器阵列的第一位线和第二位线的读出放大器的集成电路的实施例。读出放大器通常包括：锁存电路和组选择输入/输出电路，以及读取，参考电压和预充电电路。进一步描述了刷新操作的方法的实施例。作为第二数据状态读取并写入阵列的一组存储器单元的第一数据状态，而不改变锁存电路的读出节点处的读取电压，其中第二数据状态是第一数据状态的倒数。

26. 发明申请

US20130182486A1 MEMORY CELLS HAVING A COMMON GATE TERMINAL 有权
公开(公告)号：US20130182486A1
公开(公告)日：2013-07-18
申请号：US13350061
申请日：2012-01-13
申请人： Rajesh N. Gupta , Farid Nemati
发明人： Rajesh N. Gupta , Farid Nemati
IPC分类号： G11C11/21 , H01L21/8239
CPC分类号： H01L27/2454 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1608
摘要： Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

27. 发明授权

US06885581B2 Dynamic data restore in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件中的动态数据恢复
公开(公告)号：US06885581B2
公开(公告)日：2005-04-26
申请号：US10472737
申请日：2002-04-05
申请人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
发明人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
IPC分类号： G11C7/00 , G11C11/00 , G11C11/39 , H01L29/866
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
摘要翻译：使用动态操作的恢复电路（106）将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元（108），并且其中使用晶闸管（110）的内部正反馈环路在单元中恢复数据。在一个示例实现中，晶闸管（110）中的内部正反馈环路用于在晶闸管电流下降到保持电流之前恢复器件的导通状态。定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用稳定存储元件

28. 发明授权

US06872602B1 Carrier coupler for thyristor-based semiconductor device 失效
标题翻译：用于晶闸管的半导体器件的载流子耦合器
公开(公告)号：US06872602B1
公开(公告)日：2005-03-29
申请号：US10785166
申请日：2004-02-23
申请人： Farid Nemati , Badredin Fatemizadeh , Andrew Horch , Scott Robins
发明人： Farid Nemati , Badredin Fatemizadeh , Andrew Horch , Scott Robins
IPC分类号： H01L21/8242 , H01L21/8244 , H01L27/08 , H01L27/108 , H01L27/11 , H01L29/417 , H01L29/74 , H01L21/332
CPC分类号： H01L29/41716 , H01L27/0817 , H01L27/108 , H01L27/10844 , H01L27/11 , H01L29/74
摘要： Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.
摘要翻译：通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

29. 发明授权

US06828176B1 Thyristor having a first emitter with relatively lightly doped portion to the base 失效
标题翻译：晶闸管具有第一发射极，该基极具有相对轻掺杂的部分
公开(公告)号：US06828176B1
公开(公告)日：2004-12-07
申请号：US10650334
申请日：2003-08-28
申请人： Farid Nemati , Scott Robins , Andrew Horch
发明人： Farid Nemati , Scott Robins , Andrew Horch
IPC分类号： H01L21332
CPC分类号： G11C11/39 , H01L27/1203 , H01L29/0834 , H01L29/41725 , H01L29/7436
摘要： A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.
摘要翻译：基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域被掺杂，使得发射极区域相对于基极区域具有光掺杂剂浓度的轻掺杂部分。在一个实施例中，晶闸管实现在存储器电路中，其中发射极区域耦合到参考电压线，并且控制端口布置成电容耦合到晶闸管以控制其中的电流流动。在另一实施方案中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上。利用这些方法，可以严格控制晶闸管中的电流，例如用于数据存储在其中。

30. 发明授权

US06778435B1 Memory architecture for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的内存架构
公开(公告)号：US06778435B1
公开(公告)日：2004-08-17
申请号：US10170816
申请日：2002-06-12
申请人： Jin-Man Han , Farid Nemati , Seong-Ook Jeong
发明人： Jin-Man Han , Farid Nemati , Seong-Ook Jeong
IPC分类号： G11C1134
CPC分类号： G11C11/39 , G11C7/18 , G11C8/08
摘要： A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical “0” and “1.” An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.
摘要翻译：一种存储器架构，特别适用于提供一种架构来容纳一个或多个基于TCCT的存储器单元并提供参考信号。存储器架构被设计为有效地将存储的信息从存储器单元解析成逻辑值，例如逻辑“0”和“1”。示例性存储器架构包括数据块，其包括第一组一个或多个位线，其中字线一行延伸到所述一个或多个位线的第一组的第一子集。数据块还包括延伸到一个或多个位线的第一组的第二子集的字线两行。存储器单元耦合到字线一行，字线两行和位线的第一和第二子集的公共位线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式