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21. 发明授权

US07233998B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07233998B2
公开(公告)日：2007-06-19
申请号：US09816004
申请日：2001-03-22
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

22. 发明授权

US06848044B2 Circuits and methods for recovering link stack data upon branch instruction mis-speculation 失效
标题翻译：在分支指令错误猜测时恢复链路栈数据的电路和方法
公开(公告)号：US06848044B2
公开(公告)日：2005-01-25
申请号：US09801608
申请日：2001-03-08
申请人： Lee Evan Eisen , James Allan Kahle , Balaram Sinharoy , William John Starke
发明人： Lee Evan Eisen , James Allan Kahle , Balaram Sinharoy , William John Starke
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3861
摘要： A method of performing operations to a link stack including the step of performing a Pop operation from the link stack which includes the substeps of storing a first pointer value to the link stack, the first pointer value being the value of a pointer to the link stack before the Pop operation, and storing a first address including a first tag popped from the link stack. The method further includes the step of performing a Push operation to the link stack which includes the substeps of storing a second address including a second tag being Pushed into the link stack and storing a second pointer to the link stack, the second pointer being the value of the pointer to the link stack after the Push operation. The method additionally provides for the recovering of the link stack following an instruction flush which includes the substeps of comparing the first pointer value and the second value, comparing the first tag and the second tag, and replacing an address at the top of the link stack with the first address when the first and second pointers match and the first and second tags match.
摘要翻译：一种对链接堆栈执行操作的方法，包括从链路堆栈执行弹出操作的步骤，该链路栈包括将第一指针值存储到链路栈的子步骤，第一指针值是指向链路栈的指针的值并且存储包括从链接堆栈弹出的第一标签的第一地址。该方法还包括对链路堆栈执行Push操作的步骤，该链路栈包括存储第二地址的子步骤，该第二地址包括被推入到链路栈中的第二标签，并将第二指针存储到链路栈，第二指针是值在Push操作后指向链接堆栈的指针。该方法另外提供了在包括比较第一指针值和第二值的子步骤的指令刷新之后恢复链路栈，比较第一标签和第二标签，以及替换链路栈顶部的地址当第一和第二指针匹配并且第一和第二标签匹配时具有第一地址。

23. 发明授权

US06654869B1 Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling 失效
标题翻译：将组标签分配给指令组，其中组标签与该组的单个指令地址一起记录在完成表中，以便于异常处理
公开(公告)号：US06654869B1
公开(公告)日：2003-11-25
申请号：US09428399
申请日：1999-10-28
申请人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore
发明人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore
IPC分类号： G06F500
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The instruction cracking unit receives the set of fetched instructions and organizes the set of instructions into an instruction group. The dispatch and completion logic assigns a group tag to the instruction group and records the group tag in an entry of the completion table for tracking the completion status of the instructions comprising the instruction group. The dispatch and control logic may record a single instruction address in the completion table entry corresponding to the each instruction group. Preferably, the single instruction address is the instruction address of the first instruction in the instruction group. The processor may flush the instruction group in response to detecting an exception generated by an instruction in the instruction group.
摘要翻译：微处理器包括提取单元，指令分解单元以及调度和完成控制逻辑。提取单元从指令高速缓存中检索一组指令。指令解码单元接收所提取的指令集，并将该组指令组织到指令组中。调度和完成逻辑将组标签分配给指令组，并将组标记记录在完成表的条目中，以跟踪包括指令组的指令的完成状态。调度和控制逻辑可以在对应于每个指令组的完成表条目中记录单个指令地址。优选地，单指令地址是指令组中的第一指令的指令地址。响应于检测到指令组中的指令产生的异常，处理器可以刷新指令组。

24. 发明授权

US06609190B1 Microprocessor with primary and secondary issue queue 失效
标题翻译：具有主和次发行队列的微处理器
公开(公告)号：US06609190B1
公开(公告)日：2003-08-19
申请号：US09478311
申请日：2000-01-06
申请人： James Allan Kahle , Charles Roberts Moore
发明人： James Allan Kahle , Charles Roberts Moore
IPC分类号： G06F930
CPC分类号： G06F9/3865 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3857
摘要： A processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected.
摘要翻译：一种处理器和数据处理系统，适用于向发布单元发送指令。问题单元包括主要问题队列和次要问题队列。如果指令当前有资格发行执行，指令将存储在主要问题队列中。如果该指令当前不符合要发行执行的规定，则该指令存储在辅助发行队列中。如果指令取决于另一个指令的结果，则指令可以从主要问题队列移动到次要发布队列。在一个实施例中，在发出用于执行的指令之后，指令可以从主要问题队列移动到次要发布队列。在该实施例中，可以在指定持续时间内将指令维持在次要发行队列中。此后，如果指令未被拒绝，则包含指令的次要发行队列条目被解除分配。

25. 发明授权

US06543003B1 Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor 失效
标题翻译：用于在无序微处理器中进行多级挂机恢复的方法和装置
公开(公告)号：US06543003B1
公开(公告)日：2003-04-01
申请号：US09436106
申请日：1999-11-08
申请人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , Larry Scott Leitner , Kevin Franklin Reick
发明人： Michael Stephen Floyd , James Allan Kahle , Hung Qui Le , Larry Scott Leitner , Kevin Franklin Reick
IPC分类号： G06F1100
CPC分类号： G06F9/3885 , G06F9/3861 , G06F11/0757 , G06F11/1405
摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.
摘要翻译：一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。执行监视以检测挂起状况。响应于检测挂起状况，分配给多个执行单元的指令被刷新。

26. 发明授权

US06543002B1 Recovery from hang condition in a microprocessor 失效
公开(公告)号：US06543002B1
公开(公告)日：2003-04-01
申请号：US09435066
申请日：1999-11-04
申请人： James Allan Kahle , Hung Qui Le , Kevin F. Reick , David James Shippy , Larry Edward Thatcher
发明人： James Allan Kahle , Hung Qui Le , Kevin F. Reick , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1100
CPC分类号： G06F11/0721 , G06F9/3861 , G06F11/0757 , G06F11/0793 , G06F11/1405
摘要： A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch. The hang recovery unit then asserts a force reject signal to an execution unit to reject all instructions pending in the execution unit's pipeline and a flush signal to the execution unit that results in the processor flushing a set of instructions. The hang recovery unit then negates the force reject, stop completion, and stop dispatch signals to resume processor operation. In one embodiment, the recovery sequence includes entering a relaxed execution mode, such as a debug mode, a serial operation mode, or an in-order mode prior to resuming processor operation. In one embodiment, the processor advances a completion tag upon completing an instruction. In this manner the completion tag indicates the instruction that is next to complete. In one embodiment, the hang recovery sequence includes flushing the processor of an instruction set comprising all instructions with tag information greater than the completion tag. In another embodiment, all instructions with tag information greater than or equal to the completion tag are flushed.

27. 发明授权

US06477635B1 Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing 失效
标题翻译：数据处理系统包括具有真实地址标签阵列的加载/存储单元以及用于校正有效地址混叠的方法
公开(公告)号：US06477635B1
公开(公告)日：2002-11-05
申请号：US09435862
申请日：1999-11-08
申请人： James Allan Kahle , George McNeil Lattimore , Jose Angel Paredes , Larry Edward Thatcher
发明人： James Allan Kahle , George McNeil Lattimore , Jose Angel Paredes , Larry Edward Thatcher
IPC分类号： G06F1210
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/0897
摘要： A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.
摘要翻译：一种数据处理系统，包括具有加载/存储单元的处理器和用于校正有效地址混叠的方法。在处理器内的加载/存储单元中，加载和存储指令按顺序执行。加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。利用真实地址标签来校正加载/存储单元内的有效地址混叠。

28. 发明授权

US06298436B1 Method and system for performing atomic memory accesses in a processor system 失效
标题翻译：用于在处理器系统中执行原子存储器访问的方法和系统
公开(公告)号：US06298436B1
公开(公告)日：2001-10-02
申请号：US09327644
申请日：1999-06-08
申请人： James Allan Kahle , Hung Qui Le , Larry Edward Thatcher , David James Shippy
发明人： James Allan Kahle , Hung Qui Le , Larry Edward Thatcher , David James Shippy
IPC分类号： G06F9305
CPC分类号： G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3842
摘要： A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.
摘要翻译：一种用于处理器系统中的原子存储器访问的方法和系统，其中所述处理器系统能够相对于特定程序顺序发出并执行不正常的多个指令。推测性地向处理器系统的执行单元发出第一预约指令。在发行时，响应于在程序中的第一预约指令之后发生的执行单元中检测到任何先前执行的预定指令而从执行单元中刷新在程序顺序中的第一预约指令之后发生的执行单元排队的指令订购。响应于在程序顺序中的第一预约指令之前发生的执行单元排队的指令的完成，通过对第一预约指令的特定数据地址进行预约来推测地执行第一预约指令，使得预约指令相对于合作条件存储指令，以任何顺序被推测地发行和执行的这些被按顺序执行。

29. 发明授权

US5978896A Method and system for increased instruction dispatch efficiency in a superscalar processor system 失效
标题翻译：用于在超标量处理器系统中提高指令调度效率的方法和系统
公开(公告)号：US5978896A
公开(公告)日：1999-11-02
申请号：US289801
申请日：1994-08-12
申请人： James Allan Kahle , Chin-Cheng Kau , David Steven Levitan , Aubrey Deene Ogden
发明人： James Allan Kahle , Chin-Cheng Kau , David Steven Levitan , Aubrey Deene Ogden
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3885
摘要： A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.
摘要翻译：一种用于在具有指令队列的超标量处理器系统中提高指令调度效率的方法和系统，所述指令队列用于以应用指定的顺序顺序接收一组指令，以及指令调度单元，用于将指令从相关联的指令缓冲器分派到多个执行单元，基础。周期性地确定关联指令缓冲器内的指令的调度状态，并且响应于在指令缓冲器的开始处的指令的调度，剩余的指令在应用指定的顺序顺序的指令缓冲器内移动，部分组的指令通过选择性控制的多路复用电路从指令队列加载到指令缓冲器中。以这种方式，可以将附加指令分派到可用的执行单元，而不需要完全调度先前的指令组。

30. 发明授权

US5956495A Method and system for processing branch instructions during emulation in a data processing system 失效
标题翻译：用于在数据处理系统中仿真期间处理分支指令的方法和系统
公开(公告)号：US5956495A
公开(公告)日：1999-09-21
申请号：US934857
申请日：1997-09-22
申请人： James Allan Kahle , Soummya Mallick
发明人： James Allan Kahle , Soummya Mallick
IPC分类号： G06F9/32 , G06F9/455
CPC分类号： G06F9/30174 , G06F9/3879 , G06F9/45504
摘要： A series of guest instructions including at least one guest branch instruction and other guest instructions are stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each other guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt of the other guest instructions. Each entry includes an indication of a location in memory of at least one semantic routine and a condition field indicating conditions that may be set or reset by the associated guest instruction. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines. In response to detection of a conditional guest branch instruction in the series of guest instructions, a determination is made whether an entry in the multiple-entry queue associated with an instruction preceding the conditional guest branch instruction in the series has a condition field including an indication of a condition upon which the conditional branch instruction depends. If so, the indication is utilized to resolve the conditional guest branch instruction.
摘要翻译：包括至少一个客户分支指令和其他访客指令的一系列访客指令被存储在存储器中。此外，由本地指令形成并且可以用于模拟一系列访客指令的一个或多个语义例程被存储在存储器中。对于一系列访客指令中的每个其他客人指令，根据接收到其他访客指令的顺序，将条目存储在多个入口队列中。每个条目包括存储至少一个语义例程的位置的指示和指示可以由相关联的客户指令设置或重置的条件的条件字段。响应于多入口队列中的条目，通过使用条目访问和执行一个或多个语义例程中的选定的条目来在处理器中仿真一系列访客指令。响应于一系列访客指令中的条件访客分支指令的检测，确定与该系列中的条件访客分支指令之前的指令相关联的多入口队列中的条目是否具有包括指示的条件字段条件分支指令所依赖的条件。如果是，则使用该指示来解析条件访客分支指令。

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