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21. 发明授权

US08440519B2 Semiconductor structures using replacement gate and methods of manufacture 有权
公开(公告)号：US08440519B2
公开(公告)日：2013-05-14
申请号：US12778319
申请日：2010-05-12
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823864 , H01L29/1083 , H01L29/6653 , H01L29/66537 , H01L29/6659 , H01L29/78 , H01L29/7833 , H01L29/7842 , H01L29/7849
摘要： An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.

22. 发明申请

US20110134504A1 Micro-Electro-Mechanical System Tiltable Lens 有权
标题翻译：微机电系统倾斜透镜
公开(公告)号：US20110134504A1
公开(公告)日：2011-06-09
申请号：US12632040
申请日：2009-12-07
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G02B26/08 , G06F17/50 , H01L21/30
CPC分类号： G02B26/08 , B81B3/004 , B81B2201/047 , G02B7/023 , G02B26/0875
摘要： A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided.
摘要翻译：可倾斜微电机械（MEMS）系统透镜包括位于绝缘体上半导体（SOI）衬底的前表面上的微观透镜和围绕微观透镜周边的半导体边缘。位于不同高度的两个水平半导体光束设置在顶部半导体层内。可以通过在透镜边缘和两个半导体束中的一个之间施加电偏压来倾斜微观透镜，从而改变光束通过微透镜的路径。可以使用可倾斜微镜透镜的阵列来形成具有可变焦距的复合透镜。还提供了这种可倾斜MEMS透镜的设计结构。

23. 发明申请

US20100261351A1 Spacer Linewidth Control 有权
标题翻译：间隔线宽控制
公开(公告)号：US20100261351A1
公开(公告)日：2010-10-14
申请号：US12622557
申请日：2009-11-20
申请人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Paterson , Jed H. Rankin
发明人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Paterson , Jed H. Rankin
IPC分类号： H01L21/302 , H01L21/306
CPC分类号： H01L21/31144
摘要： A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.
摘要翻译：用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻的部分蚀刻的间隔材料层。用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

24. 发明授权

US06660596B2 Double planar gated SOI MOSFET structure 失效
公开(公告)号：US06660596B2
公开(公告)日：2003-12-09
申请号：US10064318
申请日：2002-07-02
申请人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
发明人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L21336
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66795
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

25. 发明授权

US06483156B1 Double planar gated SOI MOSFET structure 失效
标题翻译：双平面门控SOI MOSFET结构
公开(公告)号：US06483156B1
公开(公告)日：2002-11-19
申请号：US09526857
申请日：2000-03-16
申请人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
发明人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L2976
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66795
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.
摘要翻译：通过使用心轴浅沟槽隔离形成工艺制造双门控绝缘体上硅（SOI）MOSFET，随后是镶嵌栅极。双门控MOSFET具有狭窄的扩散线，其通过光刻或光刻和缩小限定，由STI样心轴工艺限定的镶嵌工艺。双门控SOI MOSFET增加每个布局宽度的电流驱动，并提供低导通电流。

26. 发明授权

US06940130B2 Body contact MOSFET 失效
标题翻译：体接触MOSFET
公开(公告)号：US06940130B2
公开(公告)日：2005-09-06
申请号：US10687333
申请日：2003-10-16
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

27. 发明授权

US06677645B2 Body contact MOSFET 有权
标题翻译：体接触MOSFET
公开(公告)号：US06677645B2
公开(公告)日：2004-01-13
申请号：US10061263
申请日：2002-01-31
申请人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

28. 发明授权

US07790611B2 Method for FEOL and BEOL wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US07790611B2
公开(公告)日：2010-09-07
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

29. 发明申请

US20080284021A1 Method for FEOL and BEOL Wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US20080284021A1
公开(公告)日：2008-11-20
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

30. 发明授权

US08138534B2 Anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器的防反射结构
公开(公告)号：US08138534B2
公开(公告)日：2012-03-20
申请号：US12770349
申请日：2010-04-29
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

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