专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US6018782A Flexible buffering scheme for inter-module on-chip communications 失效
标题翻译：用于片内模块间通信的灵活缓冲方案
公开(公告)号：US6018782A
公开(公告)日：2000-01-25
申请号：US892415
申请日：1997-07-14
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/78 , G06F15/80 , G06F13/38 , G06F13/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A single chip integrated circuit comprises a plurality of modules interconnected in an on-chip network. The modules are processors or memory devices or hybrids. An inter-module link provides an electrical path for data communication among the modules. The modules are connected to the inter-module link by inter-module ports, with at least one inter-module port coupled between an associated module and the inter-module link. The inter-module link electrically couples the inter-module ports and provides a communications pathway between the modules. Each inter-module port provides a common, universal interface to any of the modules, i.e., modules of different types are connectable to any inter-module port. Each inter-module port operates to receive data from the inter-module link, to determine if the data from the inter-module link is addressed to the associated module, to provide the data from the inter-module link to the associated module if the inter-module port determines that the data from the inter-module link is addressed to the associated module, to accept data from the associated module for transmission on the inter-module link, and to transmit the data from the associated module on the inter-module link. The on-chip network may also include an inter-module network switch for joining circuits of the inter-module link and routing data packets from one inter-module links to another or an inter-chip network bridge to join two single chip integrated circuits into a single communications network and route data packets from modules on one computer chip to modules on another computer chip.
摘要翻译：单芯片集成电路包括在片上网络中互连的多个模块。这些模块是处理器或存储器件或混合器。模块间链路为模块之间的数据通信提供电路。模块通过模块间端口连接到模块间链路，其中至少一个模块间端口耦合在相关联的模块和模块间链路之间。模块间链路电连接模块间端口并提供模块之间的通信路径。每个模块间端口为任何模块提供通用的通用接口，即不同类型的模块可连接到任何模块间端口。每个模块间端口操作以从模块间链路接收数据，以确定来自模块间链路的数据是否被寻址到相关联的模块，以将数据从模块间链路提供给相关联的模块，如果模块间端口确定来自模块间链路的数据被发送到相关联的模块，以接收来自相关联的模块的数据以在模块间链路上传输，并且从相关联的模块发送数据，模块链接。片上网络还可以包括用于将模块间链路的电路和从一个模块间链路到另一个或芯片间网桥的路由数据分组的模块间网络交换机，以将两个单芯片集成电路连接到单个通信网络并将数据包从一个计算机芯片上的模块路由到另一个计算机芯片上的模块。

22. 发明授权

US5908468A Data transfer network on a chip utilizing a multiple traffic circle topology 失效
标题翻译：数据传输网络利用多业务圈拓扑的芯片
公开(公告)号：US5908468A
公开(公告)日：1999-06-01
申请号：US957093
申请日：1997-10-24
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/78 , G06F15/80 , G06F13/00
CPC分类号： G06F15/78 , G06F15/8015
摘要： A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a circular topology to form preferably a plurality of traffic circles. The various modules may be processors, memories and/or hybrids and may include, or be coupled through, a communications port coupled to one of the buses such that the communications port is operable to transmit and receive data on one of the buses. Each of the communications ports is operable to route data from a source bus to a destination bus. The traffic circles are formed by groups of communications ports, and buses or groups of transfer paths. The buses may be operable to transfer data in only one direction or in two directions. The transfer of data on the buses by the modules may be controlled by an on-chip bus controller coupled to one or more of the buses. The bus controller may also include arbiter logic for arbitrating access to one or more of the plurality of buses. One or more of the plurality of communications ports may be further operable to transfer data from one of the buses to a bus connection operable to route data to a device external to computer chip. One or more of the plurality of buses includes addressing and control lines.
摘要翻译：计算机芯片包括互连在片上数据传输网络中的多个模块，其被配置成圆形拓扑结构，以优选地形成多个业务圈。各种模块可以是处理器，存储器和/或混合器，并且可以包括耦合到总线之一的通信端口，或者耦合到通信端口，使得通信端口可操作以在总线之一上发送和接收数据。每个通信端口可操作以将数据从源总线路由到目的地总线。交通圈由通信端口组，公交车组或传输路径组成。总线可以用于仅在一个方向或两个方向上传送数据。通过模块传输总线上的数据可以由耦合到一个或多个总线的片上总线控制器来控制。总线控制器还可以包括用于仲裁访问多个总线中的一个或多个的仲裁器逻辑。多个通信端口中的一个或多个可以进一步可操作以将数据从总线之一传送到可操作以将数据路由到计算机芯片外部的设备的总线连接。多个总线中的一个或多个包括寻址和控制线。

23. 发明授权

US5878265A Data transfer network on a chip utilizing polygonal hub topology 失效
标题翻译：使用多边形集线器拓扑的芯片上的数据传输网络
公开(公告)号：US5878265A
公开(公告)日：1999-03-02
申请号：US891817
申请日：1997-07-14
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8007 , G06F15/17337
摘要： A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a mesh of rings, ring or rings, or polygonal hub topology. The data transfer network includes links or buses and a switchpoint. The links or buses are configured in a ring topology as a ring of rings or polygonal hub with each group of links or bus including a portion which is shared with a portion of another group of links bus. The bus switchpoint is positioned as a hub at the intersection of the ring of rings. The switchpoint is operable to route data from a source to a destination so that the modules are operable to communicate with each other through the links or buses, and the switchpoint. In various embodiments, the modules are coupled to the links or buses and/or the switchpoint. The various modules may be processors, memories or hybrids and may include, or be coupled through, a communication port coupled to one of the links or buses such that the communication port is operable to transmit and receive data on one or more of the groups of links or buses.
摘要翻译：计算机芯片包括互连在片上数据传输网络中的多个模块，其被配置成环形，环形或环形或多边形集线器拓扑结构。数据传输网络包括链路或总线和切换点。链路或总线被配置为环形环形环或环形多边形集线器，每组链路或总线包括与另一组链路总线的一部分共享的部分。总线切换点定位为环形环交叉点处的集线器。切换点可操作以将数据从源路由到目的地，使得模块可操作以通过链路或总线以及切换点彼此通信。在各种实施例中，模块耦合到链路或总线和/或切换点。各种模块可以是处理器，存储器或混合器，并且可以包括耦合到链路或总线之一的通信端口，或者耦合到通信端口，使得通信端口可操作以在一个或多个连接或公共汽车。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式