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21. 发明授权

US09653541B2 Structure and method to make strained FinFET with improved junction capacitance and low leakage 有权
公开(公告)号：US09653541B2
公开(公告)日：2017-05-16
申请号：US14980210
申请日：2015-12-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Darsen D. Lu , Alexander Reznicek , Kern Rim
IPC分类号： H01L29/06 , H01L29/78 , H01L29/161 , H01L29/66 , H01L29/165 , H01L29/08 , H01L21/02
CPC分类号： H01L29/0638 , H01L21/02532 , H01L21/0262 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.

22. 发明申请

US20170053839A1 SEMICONDUCTOR STRUCTURES HAVING INCREASED CHANNEL STRAIN USING FIN RELEASE IN GATE REGIONS 审中-公开
公开(公告)号：US20170053839A1
公开(公告)日：2017-02-23
申请号：US14953519
申请日：2015-11-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Darsen D. Lu , Alexander Reznicek , Kern Rim
IPC分类号： H01L21/84 , H01L21/8238 , H01L21/324 , H01L29/10 , H01L21/32 , H01L29/161 , H01L21/02 , H01L29/66 , H01L21/033
CPC分类号： H01L29/6681 , H01L21/02532 , H01L21/0332 , H01L21/32 , H01L21/324 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要： A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

23. 发明申请

US20170040452A1 DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE 有权
标题翻译：具有改进的金属型材的电介质隔离结构
公开(公告)号：US20170040452A1
公开(公告)日：2017-02-09
申请号：US15332408
申请日：2016-10-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Darsen D. Lu , Ali Khakifirooz , Kern Rim
IPC分类号： H01L29/78 , H01L29/66 , H01L21/3105 , H01L21/324 , H01L21/311 , H01L21/02 , H01L29/06 , H01L21/762
CPC分类号： H01L29/7846 , H01L21/02236 , H01L21/30604 , H01L21/3086 , H01L21/31051 , H01L21/311 , H01L21/31111 , H01L21/324 , H01L21/76224 , H01L29/0653 , H01L29/1054 , H01L29/6653 , H01L29/66553 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.
摘要翻译：一种形成翅片结构的方法，其包括从体半导体衬底形成多个翅片结构，并在所述多个翅片结构中的每个翅片结构的侧壁上形成电介质间隔物。在电介质间隔物的侧壁上形成半导体衬垫。在相邻翅片结构之间的空间中形成介电填料。存在于电介质隔板的下表面下方的半导体间隔物和翅片结构的一部分被氧化。氧化翅片结构的基部产生第一应变并且氧化半导体间隔物产生与第一应变相反的第二应变。

24. 发明授权

US09543323B2 Strain release in PFET regions 有权
标题翻译：应变释放在PFET区域
公开(公告)号：US09543323B2
公开(公告)日：2017-01-10
申请号：US14595316
申请日：2015-01-13
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Darsen D. Lu , Alexander Reznicek , Kern Rim
IPC分类号： H01L21/8234 , H01L27/12 , H01L21/84 , H01L21/3065 , H01L29/161 , H01L27/092 , H01L29/66 , H01L29/78
CPC分类号： H01L27/1211 , H01L21/3065 , H01L21/76251 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L29/1054 , H01L29/161 , H01L29/42392 , H01L29/66545 , H01L29/7849
摘要： A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.
摘要翻译：一种制造半导体器件的方法，包括提供绝缘体上的应变硅（SSOI）结构，所述SSOI结构包括设置在衬底上的电介质层，设置在所述电介质层上的硅锗层和设置在所述绝缘体上的应变半导体材料层直接在硅锗层上，在SSOI结构上形成多个鳍片，在nFET区域中的至少一个鳍片的一部分上形成栅极结构，在pFET区域中的至少一个鳍片的一部分上形成栅极结构去除pFET区域中的至少一个鳍片的部分上的栅极结构，去除通过去除而暴露的硅锗层，并在pFET区域中的至少一个鳍片的部分上形成新的栅极结构，新的门结构围绕四面的部分。

25. 发明授权

US09515171B1 Radiation tolerant device structure 有权
标题翻译：辐射耐受器件结构
公开(公告)号：US09515171B1
公开(公告)日：2016-12-06
申请号：US14920046
申请日：2015-10-22
申请人： International Business Machines Corporation
发明人： Bruce B. Doris , Ali Khakifirooz , Darsen D. Lu , Philip J. Oldiges
IPC分类号： H01L21/3115 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/36
CPC分类号： H01L29/6681 , H01L21/3086 , H01L21/31155 , H01L29/66545 , H01L29/785
摘要： Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps of: forming fin masks on a SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins. Implementations with a bulk substrate, as well as the resulting devices, are also provided.
摘要翻译：提供了制造耐辐射器件结构的技术。一方面，形成辐射硬化装置的方法包括以下步骤：在SOI晶片的SOI层上形成翅片掩模，其中所述SOI晶片包括通过掩埋绝缘体与衬底分离的SOI层; 使用翅片掩模在SOI层中构图翅片; 以及将所述至少一种掺杂剂注入到所述鳍片之间的所述埋入式绝缘体的暴露部分中，以通过在所述埋入式绝缘体中提供用于耗散的掩埋绝缘体中的路径来增加所述器件结构的辐射硬度，其中在所述植入步骤期间将所述翅片掩模留在原位以防止损坏散热片。还提供了具有块体基板的实现以及所得到的器件。

26. 发明授权

US09455250B1 Distributed decoupling capacitor 有权
标题翻译：分布式去耦电容
公开(公告)号：US09455250B1
公开(公告)日：2016-09-27
申请号：US14788092
申请日：2015-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Ali Khakifirooz , Darsen D. Lu , Ghavam G. Shahidi
IPC分类号： H01L21/02 , H01L27/06 , H01L29/78 , H01L29/94 , H01L27/108 , H01L23/528 , H01L27/092 , H01L29/66 , H01L49/02 , H01L23/522 , H01L21/8238 , H01L21/768
CPC分类号： H01L27/0629 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L23/485 , H01L23/5222 , H01L23/5223 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L27/0207 , H01L27/0924 , H01L28/60 , H01L29/0847 , H01L29/66795 , H01L29/6681 , H01L29/785 , H01L29/7851 , H01L29/94
摘要： An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
摘要翻译：一种包括多个翅片结构的电气装置。多个翅片结构包括至少一个去耦翅片和至少一个半导体翅片。电气装置包括至少一个半导体器件，其包括存在于至少一个半导体鳍片中的沟道区域，存在于至少一个半导体鳍片的沟道区域上的栅极结构以及存在于源极和漏极区域部分上的源极和漏极区域的至少一个半导体鳍片。电气设备包括至少一个去耦电容器，其包括作为去耦电容器的第一电极的去耦鳍结构，节点电介质层和由金属接触件提供到半导体鳍片结构的源极和漏极区域的第二电极。去耦电容器位于电力线下方到半导体鳍结构。

27. 发明申请

US20150263091A1 LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING GRADED SiGe BASE 有权
标题翻译：具有分级SiGe基底的横向双极晶体管
公开(公告)号：US20150263091A1
公开(公告)日：2015-09-17
申请号：US14208518
申请日：2014-03-13
申请人： International Business Machines Corporation
发明人： Pouya Hashemi , Ali Khakifirooz , Darsen D. Lu , Alexander Reznicek , Dominic J. Schepis
IPC分类号： H01L29/10 , H01L21/225 , H01L29/06 , H01L29/66 , H01L29/735
CPC分类号： H01L29/1008 , H01L21/2254 , H01L21/8249 , H01L27/0623 , H01L27/0924 , H01L29/0692 , H01L29/0808 , H01L29/0821 , H01L29/41708 , H01L29/4232 , H01L29/6625 , H01L29/66795 , H01L29/735 , H01L29/785
摘要： A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.
摘要翻译：使用绝缘体上半导体衬底制造横向双极结晶体管。晶体管包括在掺杂硅基区内的锗梯度，晶体管的集电极区域的方向上锗含量增加。使用包括平行硅散热片的衬底来制造横向双极结晶体管有助于将CMOS FinFET器件和具有分级硅锗基极区域的横向双极结型晶体管包括在同一芯片上。

28. 发明申请

US20150255606A1 STRUCTURE AND METHOD TO MAKE STRAINED FINFET WITH IMPROVED JUNCTION CAPACITANCE AND LOW LEAKAGE 有权
标题翻译：具有改善的结电容和低漏电的应变FINFET的结构和方法
公开(公告)号：US20150255606A1
公开(公告)日：2015-09-10
申请号：US14202525
申请日：2014-03-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Darsen D. Lu , Alexander Reznicek , Kern Rim
IPC分类号： H01L29/78 , H01L21/02 , H01L21/28 , H01L21/306 , H01L29/66 , H01L29/06
CPC分类号： H01L29/0638 , H01L21/02532 , H01L21/0262 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method of forming a semiconductor device that includes forming a gate structure on a fin structure and etching the source and drain region portions of the fin structure to provide a recessed surface. A first semiconductor layer is formed on the recessed surface of the fin structure that is doped to a first conductivity type. A leakage barrier layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the leakage barrier layer. The second semiconductor layer is doped to a second conductivity type.
摘要翻译：一种形成半导体器件的方法，包括在鳍结构上形成栅极结构并蚀刻鳍结构的源极和漏极区域以提供凹陷表面。第一半导体层形成在鳍状结构的凹入表面上，该第一半导体层被掺杂到第一导电类型。在第一半导体层上形成漏电阻层。在漏电阻层上形成第二半导体层。第二半导体层被掺杂到第二导电类型。

29. 发明申请

US20150243755A1 DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE 有权
标题翻译：具有改进的金属型材的电介质隔离结构
公开(公告)号：US20150243755A1
公开(公告)日：2015-08-27
申请号：US14189294
申请日：2014-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Darsen D. Lu , Ali Khakifirooz , Kern Rim
IPC分类号： H01L29/66 , H01L21/311 , H01L29/78
CPC分类号： H01L29/7846 , H01L21/02236 , H01L21/30604 , H01L21/3086 , H01L21/31051 , H01L21/311 , H01L21/31111 , H01L21/324 , H01L21/76224 , H01L29/0653 , H01L29/1054 , H01L29/6653 , H01L29/66553 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.
摘要翻译：一种形成翅片结构的方法，其包括从体半导体衬底形成多个翅片结构，并在所述多个翅片结构中的每个翅片结构的侧壁上形成电介质间隔物。在电介质间隔物的侧壁上形成半导体衬垫。在相邻翅片结构之间的空间中形成介电填料。存在于电介质隔板的下表面下方的半导体间隔物和翅片结构的一部分被氧化。氧化翅片结构的基部产生第一应变并且氧化半导体间隔物产生与第一应变相反的第二应变。

30. 发明授权

US10903208B2 Distributed decoupling capacitor 有权
公开(公告)号：US10903208B2
公开(公告)日：2021-01-26
申请号：US16739754
申请日：2020-01-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Ali Khakifirooz , Darsen D. Lu , Ghavam G. Shahidi
IPC分类号： H01L21/768 , H01L27/06 , H01L23/528 , H01L27/092 , H01L29/66 , H01L29/78 , H01L49/02 , H01L23/522 , H01L21/8238 , H01L29/94 , H01L21/84 , H01L27/12 , H01L21/8234 , H01L27/02 , H01L29/08 , H01L23/485
摘要： An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

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