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21. 发明授权

US08339895B2 Signal calibration methods and apparatuses 有权
标题翻译：信号校准方法和装置
公开(公告)号：US08339895B2
公开(公告)日：2012-12-25
申请号：US13061519
申请日：2009-08-27
申请人： Frederick A. Ware , Reza Navid , John W. Poulton
发明人： Frederick A. Ware , Reza Navid , John W. Poulton
IPC分类号： G11C8/18
CPC分类号： H03L7/00
摘要： In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.
摘要翻译：在信号校准方案中，在一组信号之间保持期望的相位关系。例如，在一些方面，可以通过检测低速参考时钟信号和与时钟树的不同相位相关联的低速时钟信号之间的相位差来维持从高速参考时钟信号产生的时钟树的期望相位。在某些方面，通过检测通过使用时钟树发生的成帧偏移，可以维持时钟树的所需相位。

22. 发明授权

US08310872B2 Multi-page parallel program flash memory 有权
标题翻译：多页并行程序闪存
公开(公告)号：US08310872B2
公开(公告)日：2012-11-13
申请号：US12863409
申请日：2009-01-16
申请人： Yoshihito Koya , Gary B. Bronner , Frederick A. Ware
发明人： Yoshihito Koya , Gary B. Bronner , Frederick A. Ware
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/24
摘要： A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.
摘要翻译：具有位线和与其耦合的多个存储单元的NAND快闪存储器件。编程电路同时耦合到多个存储单元，以对与相同位线相关联的不同NAND串中的两个或更多个存储单元进行编程。

23. 发明授权

US08295107B2 Asynchronous pipelined memory access 失效
标题翻译：异步流水线内存访问
公开(公告)号：US08295107B2
公开(公告)日：2012-10-23
申请号：US13281436
申请日：2011-10-26
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.
摘要翻译：多个控制信号在异步集成电路存储器件内响应于存储器访问启动信号的每个转换而被执行以实现流水线存储器访问操作。

24. 发明申请

US20120262998A1 CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的时钟同步
公开(公告)号：US20120262998A1
公开(公告)日：2012-10-18
申请号：US13446703
申请日：2012-04-13
申请人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
发明人： Jade M. Kizer , John M. Wilson , John Eble, III , Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.
摘要翻译：在存储器系统中提供同步。在存储器写入操作期间，通过控制信号将定时参考信号发送到存储器件，并且从存储器件接收校准信号。根据校准信号调整内部时钟信号，然后根据内部时钟发送数据信号。以这种方式，数据被同步，使得数据根据本地时钟信号被精确地采样。

25. 发明申请

US20120254472A1 CHIP SELECTION IN A SYMMETRIC INTERCONNECTION TOPOLOGY 审中-公开
标题翻译：芯片选择在对称互连拓扑学中
公开(公告)号：US20120254472A1
公开(公告)日：2012-10-04
申请号：US13514977
申请日：2010-12-07
申请人： Frederick A. Ware , Brian S. Leibowitz
发明人： Frederick A. Ware , Brian S. Leibowitz
IPC分类号： G06F3/00
CPC分类号： G06F13/1684 , G11C5/02
摘要： Techniques for distinguishing between symmetrically-connected integrated circuit devices so that each device may be individually selected are disclosed in reference to various embodiments. In one embodiment, a bi-directional data path provided for ongoing data transfer between a master device and multiple nominally identical slave devices is used to receive a merged set of randomly generated values from the slave devices, and then used to return one or more device-select values that enable assignment of a unique chip-identifier (ID) within each slave device. After chip-IDs have been assigned to the slave devices, the master device may issue one or more chip-select signals corresponding to the unique chip ID assigned to a given slave and thereby enable that slave device, exclusively of the others, to participate in a data transfer operation over the bi-directional data path.
摘要翻译：用于区分对称连接的集成电路器件以便可以单独选择每个器件的技术参考各种实施例来公开。在一个实施例中，提供用于主设备和多个名义上相同的从设备之间的正在进行的数据传输的双向数据路径用于从从设备接收随机生成的值的合并集合，然后用于返回一个或多个设备 - 选择允许在每个从设备中分配唯一的芯片标识符（ID）的值。在将芯片ID分配给从设备之后，主设备可以发出与分配给给定从设备的唯一芯片ID相对应的一个或多个芯片选择信号，从而使得其他专用设备能够参与在双向数据路径上的数据传输操作。

26. 发明申请

US20120243632A1 PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE 有权
标题翻译：固定时钟接口的部分速率传输模式
公开(公告)号：US20120243632A1
公开(公告)日：2012-09-27
申请号：US13491479
申请日：2012-06-07
申请人： Frederick A. Ware , Robert E. Palmer , John Poulton
发明人： Frederick A. Ware , Robert E. Palmer , John Poulton
IPC分类号： H04L7/04
CPC分类号： H04L7/0337 , G06F13/4243 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2227 , H03L7/06 , H04L7/0008 , H04L7/046 , Y02D10/14 , Y02D10/151
摘要： Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.
摘要翻译：为使用固定时钟速率接口的部分速率传输模式提供了系统和方法。在部分速率模式下，每个数据位连续传输两次或更多次。接收机使用不进行相位调整的全局时钟来检测复制的传入位。结果，当系统锁定到从发射机接收的数据的相位时，接收机系统可以以部分数据速率接收数据。

27. 发明授权

US08261039B2 Memory controllers, methods, and systems supporting multiple memory modes 有权
标题翻译：支持多种内存模式的内存控制器，方法和系统
公开(公告)号：US08261039B2
公开(公告)日：2012-09-04
申请号：US12820973
申请日：2010-06-22
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00 , G11C7/00 , G11C29/00
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

28. 发明申请

US20120201068A1 STACKED SEMICONDUCTOR DEVICE 有权
标题翻译：堆叠半导体器件
公开(公告)号：US20120201068A1
公开(公告)日：2012-08-09
申请号：US13502093
申请日：2010-09-24
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G11C5/06 , H01L21/50 , H01L23/522
CPC分类号： G11C11/4093 , G11C5/04 , G11C11/4096 , G11C17/16 , G11C17/18 , H01L24/05 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L2224/05552 , H01L2224/05568 , H01L2224/08148 , H01L2224/8013 , H01L2224/80132 , H01L2224/80897 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.
摘要翻译：公开了一种包括多个半导体管芯的叠层半导体器件。每个模具具有相对设置的第一和第二表面，在每个表面上形成有垫。多个通孔将第一表面上的相应焊盘连接到第二表面上的相应焊盘。通孔包括耦合到半导体管芯上的相应I / O电路的第一组通孔，以及未耦合到半导体管芯上的I / O电路的第二组通孔。多个半导体管芯被堆叠，使得多个半导体管芯中的第一个半导体管芯中的第一组通孔与第二组通孔中的至少一部分中的相应的通孔对准多个半导体管芯。

29. 发明授权

US08218382B2 Memory component having a write-timing calibration mode 有权
标题翻译：具有写定时校准模式的存储器组件
公开(公告)号：US08218382B2
公开(公告)日：2012-07-10
申请号：US13228070
申请日：2011-09-08
申请人： Frederick A. Ware
发明人： Frederick A. Ware
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/10 , G06F13/1689 , G06F13/4243 , G11C7/1072 , G11C7/22 , G11C8/18 , G11C11/409 , G11C2207/2254
摘要： In memory component having a write-timing calibration mode, control information that specifies a write operation is received via a first external signal path and write data corresponding to the write operation is received via a second external signal path. The memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid write data, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the first external signal path and outputting the write data on the second external signal path.
摘要翻译：在具有写入定时校准模式的存储器组件中，经由第一外部信号路径接收指定写入操作的控制信息，并且经由第二外部信号路径接收与写入操作相对应的写入数据。存储器组件接收用于指示写入数据是有效写入数据的定时信号的多个延迟版本，并且输出与定时信号的多个延迟版本对应的信号，以使得能够在存储器控制器中确定输出关于第一外部信号路径的控制信息，并在第二外部信号路径上输出写入数据。

30. 发明申请

US20120173811A1 Method and Apparatus for Delaying Write Operations 审中-公开
标题翻译：延迟写入操作的方法和装置
公开(公告)号：US20120173811A1
公开(公告)日：2012-07-05
申请号：US13421753
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

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