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21. 发明授权

US08178433B2 Methods for the formation of fully silicided metal gates 有权
标题翻译：形成完全硅化金属门的方法
公开(公告)号：US08178433B2
公开(公告)日：2012-05-15
申请号：US12246921
申请日：2008-10-07
申请人： Glenn A. Biery , Michelle L. Steen
发明人： Glenn A. Biery , Michelle L. Steen
IPC分类号： H01L21/3205
CPC分类号： H01L29/6656 , H01L21/823425 , H01L21/823443 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.
摘要翻译：提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。还提供了形成高级门结构的方法。

22. 发明申请

US20090029515A1 METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES 有权
标题翻译：形成完全硅化金属栅的方法
公开(公告)号：US20090029515A1
公开(公告)日：2009-01-29
申请号：US12246921
申请日：2008-10-07
申请人： Glenn A. Biery , Michelle L. Steen
发明人： Glenn A. Biery , Michelle L. Steen
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823425 , H01L21/823443 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.
摘要翻译：提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。还提供了形成高级门结构的方法。

23. 发明授权

US08080876B2 Structure and method for creating reliable deep via connections in a silicon carrier 有权
标题翻译：用于在硅载体中创建可靠的深通孔连接的结构和方法
公开(公告)号：US08080876B2
公开(公告)日：2011-12-20
申请号：US12147466
申请日：2008-06-26
申请人： Paul S. Andry , John U. Knickerbocker , Michelle L. Steen , Cornelia K. Tsang
发明人： Paul S. Andry , John U. Knickerbocker , Michelle L. Steen , Cornelia K. Tsang
IPC分类号： H01L23/538
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译：一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

24. 发明授权

US07705405B2 Methods for the formation of fully silicided metal gates 有权
标题翻译：形成完全硅化金属门的方法
公开(公告)号：US07705405B2
公开(公告)日：2010-04-27
申请号：US10885462
申请日：2004-07-06
申请人： Glenn A. Biery , Michelle L. Steen
发明人： Glenn A. Biery , Michelle L. Steen
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823425 , H01L21/823443 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of forming the advanced gate structure are also provided.
摘要翻译：提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。还提供了形成高级门结构的方法。

25. 发明申请

US20090039472A1 STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER 有权
标题翻译：通过硅载体连接创造可靠深度的结构和方法
公开(公告)号：US20090039472A1
公开(公告)日：2009-02-12
申请号：US12147466
申请日：2008-06-26
申请人： Paul S. Andry , John U. Knickerbocker , Michelle L. Steen , Cornelia K. Tsang
发明人： Paul S. Andry , John U. Knickerbocker , Michelle L. Steen , Cornelia K. Tsang
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译：一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

26. 发明授权

US07014959B2 CD uniformity of chrome etch to photomask process 失效
标题翻译：铬蚀刻到光掩模工艺的CD均匀性
公开(公告)号：US07014959B2
公开(公告)日：2006-03-21
申请号：US10605801
申请日：2003-10-28
申请人： Shaun B. Crawford , Timothy J. Dalton , Thomas B. Faure , Cuc K. Huynh , Michelle L. Steen , Thomas M. Wagner
发明人： Shaun B. Crawford , Timothy J. Dalton , Thomas B. Faure , Cuc K. Huynh , Michelle L. Steen , Thomas M. Wagner
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： C23F4/00 , G03F1/80 , H01L21/0332 , H01L21/32136
摘要： A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibits a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.
摘要翻译：通过在透明基底上沉积不透明层而形成光掩模。抗蚀剂形成在不透明层上并选择性地图案化以暴露待被蚀刻出的不透明层的部分。在干蚀刻步骤期间，光掩模暴露于在不透明层和抗蚀剂层之间具有等于或高于1.2:1的选择性的蚀刻剂气体混合物。由于气体混合物的选择性，可以使用更薄的抗蚀剂膜，从而提高不透明层图案的分辨率和精度。此外，由于对宏观负载效应和图案密度效应的敏感性降低，抗蚀剂的过蚀刻和不透明层的去抛光显着降低，从而实现了改进的蚀刻均匀性并因此改善了CD均匀性。

27. 发明申请

US20080179755A1 STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER 审中-公开
标题翻译：通过硅载体连接创造可靠深度的结构和方法
公开(公告)号：US20080179755A1
公开(公告)日：2008-07-31
申请号：US11669924
申请日：2007-01-31
申请人： Paul S. Andry , L. Paivikki Buchwalter , Anurag Jain , John U. Knickerbocker , Edmund J. Sprogis , Michelle L. Steen , Cornelia K. Tsang
发明人： Paul S. Andry , L. Paivikki Buchwalter , Anurag Jain , John U. Knickerbocker , Edmund J. Sprogis , Michelle L. Steen , Cornelia K. Tsang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译：一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

28. 发明授权

US07273777B2 Formation of fully silicided (FUSI) gate using a dual silicide process 失效
标题翻译：使用双重硅化物工艺形成完全硅化（FUSI）栅极
公开(公告)号：US07273777B2
公开(公告)日：2007-09-25
申请号：US11195994
申请日：2005-08-02
申请人： Glenn A. Biery , Ghavam Shahidi , Michelle L. Steen
发明人： Glenn A. Biery , Ghavam Shahidi , Michelle L. Steen
IPC分类号： H01L21/8238 , H01L21/4763
CPC分类号： H01L29/6656 , H01L21/28097 , H01L21/28518 , H01L29/51 , H01L29/66545
摘要： A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.
摘要翻译：一种形成半导体器件结构的方法，包括以下步骤：在多晶硅栅叠层中独立地形成源极/漏极表面金属硅化物层和完全硅化金属栅极。具体地说，在形成源极/漏极表面金属硅化物层之后并且在形成硅化金属栅极之前，在多晶硅栅极堆叠的侧壁上提供一组或多组间隔结构，以防止在其中形成附加的金属硅化物结构源极/漏极区域在栅极盐化过程中。所得到的半导体器件结构包括完全硅化物金属栅极，该栅极或者包含与源/漏表面金属硅化物层中的不同的金属硅化物材料，或者具有比源极/漏极表面金属硅化物层的厚度更大的厚度。除了表面金属硅化物层之外，半导体器件结构的源极/漏极区域没有其它金属硅化物结构。

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