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21. 发明授权

US08865556B2 Using fast anneal to form uniform Ni(Pt)Si(Ge) contacts on SiGe layer 有权
标题翻译：使用快速退火在SiGe层上形成均匀的Ni（Pt）Si（Ge）接触
公开(公告)号：US08865556B2
公开(公告)日：2014-10-21
申请号：US13611893
申请日：2012-09-12
申请人： Joseph S. Newbury , Kenneth Parker Rodbell , Zhen Zhang , Yu Zhu
发明人： Joseph S. Newbury , Kenneth Parker Rodbell , Zhen Zhang , Yu Zhu
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/02
CPC分类号： H01L21/28518 , H01L29/45 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
摘要翻译：提供了不使用盖层形成光滑硅化物的技术。一方面，提供一种FET器件。 FET器件包括在BOX上具有SOI层的SOI晶片和形成在晶片中的至少一个有源区域; 所述至少一个有效区域的一部分上的栅极堆叠，其用作所述装置的通道; 源极和漏极区域，其中该器件的源极和漏极区域包括选自硅和硅锗的半导体材料; 并且硅化物接触到器件的源极和漏极区域，其中在硅化物触点和半导体材料之间存在界面，并且其中界面的界面粗糙度小于约5纳米。

22. 发明申请

US20140005059A1 BIOMARKERS FOR CANCER 审中-公开
标题翻译：癌症生物标志物
公开(公告)号：US20140005059A1
公开(公告)日：2014-01-02
申请号：US12530456
申请日：2009-09-08
申请人： Zhen Zhang , Jin Song , Daniel Wan- Yui Chan
发明人： Zhen Zhang , Jin Song , Daniel Wan- Yui Chan
IPC分类号： G01N33/574
CPC分类号： G01N33/57449 , G01N33/574
摘要： The instant invention provides methods and compositions for the diagnosis and treatment of cancer. The invention also provides method and compositions for determining if a subject is, or is at risk of becoming, chemoresistant.
摘要翻译：本发明提供了用于诊断和治疗癌症的方法和组合物。本发明还提供了用于确定受试者是否具有成为化疗耐药性的风险的方法和组合物。

23. 发明申请

US20140000712A1 NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS 有权
标题翻译：用于薄膜太阳能电池的氮化硅薄膜应力层
公开(公告)号：US20140000712A1
公开(公告)日：2014-01-02
申请号：US13534519
申请日：2012-06-27
申请人： Qing Cao , Zhengwen Li , Fei Liu , Zhen Zhang
发明人： Qing Cao , Zhengwen Li , Fei Liu , Zhen Zhang
IPC分类号： H01L31/0264 , H01L31/18
CPC分类号： H01L31/02167 , H01L31/022425 , H01L31/022441 , H01L31/022475 , H01L31/0296 , H01L31/0322 , H01L31/0326 , H01L31/0749 , Y02E10/541 , Y02P70/521
摘要： A method of forming a photovoltaic device includes forming a thermal stress relieving layer on top of a substrate and forming a sacrificial back electrode metal layer on the thermal stress relieving layer. A semiconductor photon absorber layer is formed on the sacrificial back electrode metal layer, and the absorber layer is reacted with substantially an entire thickness of the sacrificial back electrode metal layer, thereby forming a back ohmic contact comprising a metallic compound of the sacrificial back electrode metal layer and the absorber layer, in combination with the thermal stress relieving layer.
摘要翻译：形成光伏器件的方法包括在衬底的顶部形成热应力消除层，并在热应力消除层上形成牺牲背电极金属层。在牺牲背电极金属层上形成半导体光子吸收层，吸收层与牺牲背极金属层的大致整个厚度反应，形成包含牺牲背电极金属的金属化合物的反欧姆接触层和吸收层，与热应力消除层组合。

24. 发明授权

US08557693B2 Contact resistivity reduction in transistor devices by deep level impurity formation 有权
标题翻译：深层杂质形成对晶体管器件的接触电阻率降低
公开(公告)号：US08557693B2
公开(公告)日：2013-10-15
申请号：US12793046
申请日：2010-06-03
申请人： Tak Hung Ning , Zhen Zhang
发明人： Tak Hung Ning , Zhen Zhang
IPC分类号： H01L21/22
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/456 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.
摘要翻译：在半导体器件中形成低电阻接触结构的方法包括在半导体衬底中形成掺杂半导体区域; 在所述掺杂半导体区域的上部形成深层杂质区域; 通过退火激活掺杂半导体区域和深层杂质区域中的掺杂剂; 以及在深层杂质区上形成金属接触，从而在它们之间产生金属 - 半导体界面。

25. 发明申请

US20130249099A1 Techniques to Form Uniform and Stable Silicide 有权
公开(公告)号：US20130249099A1
公开(公告)日：2013-09-26
申请号：US13428184
申请日：2012-03-23
申请人： Christian Lavoie , Dong-Ick Lee , Ahmet Serkan Ozcan , Zhen Zhang
发明人： Christian Lavoie , Dong-Ick Lee , Ahmet Serkan Ozcan , Zhen Zhang
IPC分类号： H01L23/48 , H01L21/336 , H01L21/28
CPC分类号： H01L29/665 , H01L21/02381 , H01L21/02631 , H01L21/244 , H01L21/28518 , H01L21/32133 , H01L21/324 , H01L29/161
摘要： In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

26. 发明申请

US20130200443A1 Interface Engineering to Optimize Metal-III-V Contacts 有权
标题翻译：接口工程优化金属III-V触点
公开(公告)号：US20130200443A1
公开(公告)日：2013-08-08
申请号：US13368750
申请日：2012-02-08
申请人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
发明人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
IPC分类号： H01L29/78 , H01L23/48 , H01L21/336 , H01L21/22
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/20 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L2924/0002 , H01L2924/00
摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
摘要翻译：提供了在III-V FET器件中制造自对准触点的技术。一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。在III-V材料的表面上沉积至少一种金属。所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。蚀刻用于去除至少一种金属的任何未反应部分。将至少一种杂质注入到金属III-V合金层中。注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。

27. 发明授权

US08470628B2 Methods to fabricate silicide micromechanical device 有权
标题翻译：制造硅化物微机械装置的方法
公开(公告)号：US08470628B2
公开(公告)日：2013-06-25
申请号：US13164126
申请日：2011-06-20
申请人： Michael A Guillorn , Eric A Joseph , Fei Liu , Zhen Zhang
发明人： Michael A Guillorn , Eric A Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01L21/66
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a silicon layer disposed over an insulating layer that is disposed on a silicon substrate; releasing a portion of the silicon layer from the insulating layer so that it is at least partially suspended over a cavity in the insulating layer; depositing a metal (e.g., Pt) on at least one surface of at least the released portion of the silicon layer and, using a thermal process, fully siliciding at least the released portion of the silicon layer using the deposited metal. The method eliminates silicide-induced stress to the released Si member, as the entire Si member is silicided. Furthermore no conventional wet chemical etch is used after forming the fully silicided material thereby reducing a possibility of causing corrosion of the silicide and an increase in stiction.
摘要翻译：公开了一种制造诸如MEMS或NEMS开关的机电装置的方法。该方法包括提供设置在设置在硅衬底上的绝缘层上的硅层; 从所述绝缘层释放所述硅层的一部分，使得其至少部分地悬挂在所述绝缘层中的空腔上; 在至少所述硅层的释放部分的至少一个表面上沉积金属（例如Pt），并且使用热处理，使用沉积的金属至少完全硅化硅层的释放部分。当整个Si元件被硅化时，该方法消除了对释放的Si元件的硅化物引起的应力。此外，在形成完全硅化材料之后，也不使用常规的湿化学蚀刻，从而减少引起硅化物腐蚀和粘性增加的可能性。

28. 发明申请

US20130115732A1 Method to Fabricate Multicrystal Solar Cell with Light Trapping Surface Using Nanopore Copolymer 有权
标题翻译：使用纳米孔共聚物制造具有光捕获表面的多晶太阳能电池的方法
公开(公告)号：US20130115732A1
公开(公告)日：2013-05-09
申请号：US13289324
申请日：2011-11-04
申请人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang
发明人： Dechao Guo , Zhengwen Li , Kejia Wang , Zhen Zhang
IPC分类号： H01L31/18 , B32B33/00 , C23F1/04
CPC分类号： H01L31/02363 , Y02E10/50
摘要： Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm.
摘要翻译：提供多晶硅加工技术。一方面，提供了一种使多晶硅表面粗糙化的方法。该方法包括以下步骤。多晶硅表面涂有二嵌段共聚物。将二嵌段共聚物退火以在其中形成纳米孔。通过二嵌段共聚物中的纳米孔蚀刻多晶硅表面以粗糙化多晶硅表面。除去二嵌段共聚物。还提供了具有多个峰和谷的具有粗糙表面的多晶硅衬底，其中粗糙表面上的一个峰到相邻峰的距离为约20nm至约400nm。

29. 发明申请

US20130020183A1 Silicide Micromechanical Device and Methods to Fabricate Same 有权
标题翻译：硅化物微机械装置及其制造方法
公开(公告)号：US20130020183A1
公开(公告)日：2013-01-24
申请号：US13625294
申请日：2012-09-24
申请人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
发明人： Michael A. Guillorn , Eric A. Joseph , Fei Liu , Zhen Zhang
IPC分类号： H01H59/00
CPC分类号： B81C1/00666 , B81C1/00952 , H01H1/0094 , H01H2001/0078
摘要： A miniaturized electro-mechanical switch includes a moveable portion having a contact configured to make, when the switch is actuated, an electrical connection between two stationary points. At least the contact is composed of a fully silicided material. A structure includes a silicon layer formed over an insulator layer and a micromechanical switch formed at least partially within the silicon layer. The micromechanical switch has a conductive structure, and where at least electrically contacting portions of the conductive structure are comprised of fully silicided material.
摘要翻译：小型化机电开关包括具有触点的可移动部分，该触点构造成当开关被致动时使得两个静止点之间的电连接。至少接触由完全硅化的材料组成。一种结构包括形成在绝缘体层上的硅层和至少部分地形成在硅层内的微机电开关。微机械开关具有导电结构，并且其中导电结构的至少电接触部分由完全硅化材料构成。

30. 发明申请

US20120285517A1 SCHOTTKY BARRIER SOLAR CELLS WITH HIGH AND LOW WORK FUNCTION METAL CONTACTS 审中-公开
标题翻译： SCHOTTKY BARRIER太阳能电池具有高低功能金属接触
公开(公告)号：US20120285517A1
公开(公告)日：2012-11-15
申请号：US13103490
申请日：2011-05-09
申请人： Joel P. de Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Conal Eugene Murray , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi , Zhen Zhang
发明人： Joel P. de Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Conal Eugene Murray , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi , Zhen Zhang
IPC分类号： H01L31/108 , H01L31/18
CPC分类号： H01L31/07 , H01L31/0321 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures.
摘要翻译：一种肖特基势垒太阳能电池，其具有设置在轻掺杂的吸收材料的前表面或后表面上的低功函数区域和高功函数区域中的至少一个，其可以以各种不同的几何形状生产。生产肖特基势垒太阳能电池的方法允许短的处理时间和低温的使用。

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