专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050286323A1 Semiconductor memory device and circuit layout of dummy cell 有权
标题翻译：半导体存储器件和虚拟电池的电路布局
公开(公告)号：US20050286323A1
公开(公告)日：2005-12-29
申请号：US11156706
申请日：2005-06-21
申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
发明人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
IPC分类号： G11C7/08 , G11C7/12 , G11C11/413 , G11C29/00
CPC分类号： G11C7/08 , G11C7/12 , G11C7/227 , G11C11/413
摘要： A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.
摘要翻译：虚拟单元包括两个串联的截止状态晶体管，由这两个晶体管形成的串联电路的一端与恒定电压源连接，串联电路的另一端与复制位线连接。这抑制了从复制位线流向虚拟单元的泄漏电流，从而给读出放大器电路提供了最佳的启动时序。

22. 发明授权

US06944003B2 Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
标题翻译：具有电压检测电路和信号发射和接收系统的半导体集成电路
公开(公告)号：US06944003B2
公开(公告)日：2005-09-13
申请号：US10365527
申请日：2003-02-13
申请人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
发明人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
IPC分类号： G01R31/28 , H01L21/66 , H02H9/04 , H02H3/24
CPC分类号： H02H9/046
摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.
摘要翻译：第一半导体集成电路通过电缆连接到第二半导体集成电路。在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作强制。因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。因此，在低电压条件下可以进行运行评估。

23. 发明授权

US06297675B1 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
标题翻译：具有串行可互连数据总线的半导体集成电路和半导体集成电路系统
公开(公告)号：US06297675B1
公开(公告)日：2001-10-02
申请号：US09478530
申请日：2000-01-06
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
IPC分类号： H03B100
CPC分类号： H03K19/018514 , Y10T307/549
摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.
摘要翻译：在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。第一芯片包括输出电路和用于控制输出电路的控制器。第二芯片包括输入电路。例如，输出电路将电流从电源提供给数据线之一。然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。随后，输出电路将反馈的直流电流提供给选通线之一。作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。然后将反馈电流排到地面。因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

24. 发明授权

US06236251B1 Semiconductor integrated circuit with multiple selectively activated synchronization circuits 失效
标题翻译：具有多个选择性激活的同步电路的半导体集成电路
公开(公告)号：US06236251B1
公开(公告)日：2001-05-22
申请号：US09261685
申请日：1999-03-03
申请人： Hironori Akamatsu
发明人： Hironori Akamatsu
IPC分类号： H03L700
CPC分类号： G11C7/222 , G06F1/10 , G11C7/1072 , G11C7/22 , H03L7/07 , H03L7/0812
摘要： A semiconductor integrated circuit provided on a semiconductor chip includes a first synchronization circuit for receiving an external clock signal supplied from outside the semiconductor chip and outputting a first internal clock signal synchronized with the external clock signal and usable inside the semiconductor chip; a second synchronization circuit for receiving the first internal clock signal and outputting a second internal clock signal synchronized with the first internal clock signal and usable inside the semiconductor chip; and a functional block operable in synchronization with the second internal clock signal.
摘要翻译：设置在半导体芯片上的半导体集成电路包括：第一同步电路，用于接收从半导体芯片外部提供的外部时钟信号，并输出与外部时钟信号同步的第一内部时钟信号，并可在半导体芯片的内部使用; 第二同步电路，用于接收第一内部时钟信号并输出与第一内部时钟信号同步的第二内部时钟信号，并可在半导体芯片内使用; 以及与第二内部时钟信号同步操作的功能块。

25. 发明授权

US06215192B1 Integrated circuit package and integrated circuit package control system 失效
标题翻译：集成电路封装和集成电路封装控制系统
公开(公告)号：US06215192B1
公开(公告)日：2001-04-10
申请号：US09095211
申请日：1998-06-10
申请人： Takashi Hirata , Hironori Akamatsu
发明人： Takashi Hirata , Hironori Akamatsu
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/16145 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/48624 , H01L2224/48724 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The integrated circuit package of this invention includes a first integrated circuit chip and a second integrated circuit chip having a same function, wherein the first integrated circuit chip and the second integrated circuit chip are connected to a common bus.
摘要翻译：本发明的集成电路封装包括具有相同功能的第一集成电路芯片和第二集成电路芯片，其中第一集成电路芯片和第二集成电路芯片连接到公共总线。

26. 发明授权

US06201412B1 Semiconductor integrated circuit with driver stabilization using parasitic capacitance 失效
标题翻译：具有驱动器稳定的半导体集成电路使用寄生电容
公开(公告)号：US06201412B1
公开(公告)日：2001-03-13
申请号：US09123902
申请日：1998-07-28
申请人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
发明人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01707
摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.
摘要翻译：本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

27. 发明申请

US20090201745A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090201745A1
公开(公告)日：2009-08-13
申请号：US12425018
申请日：2009-04-16
申请人： Satoshi ISHIKURA , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
发明人： Satoshi ISHIKURA , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
IPC分类号： G11C7/00 , G11C29/00 , G11C5/14
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译：半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。

28. 发明申请

US20070133326A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070133326A1
公开(公告)日：2007-06-14
申请号：US11634110
申请日：2006-12-06
申请人： Satoshi Ishikura , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
发明人： Satoshi Ishikura , Hironori Akamatsu , Kazuo Itoh , Yoshinobu Yamagami
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/1202 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied to bit lines 106 and 107; a latch potential control circuit 101 for switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potential supplied to the sources of the load transistors 108 and 111 to be lower than at least one of the potential supplied to the word line 105 and the potential supplied to the bit lines 106 and 107, during an arbitrary period of at least a read operation in the test mode.
摘要翻译：半导体存储器件包括具有电路结构的存储单元，其中提供给包含在锁存部分中的负载晶体管108和111的源极的电位与提供给字线105的电位和提供给字线105的电位中的至少一个不同位线106和107; 锁存电位控制电路101，用于根据施加到测试模式设置引脚102的信号将正常操作模式和测试模式切换到彼此; 以及用于控制提供给负载晶体管108和111的源的电位低于提供给字线105的电位和提供给位线106和107的电位中的至少一个的读/写控制电路103 在测试模式下至少读取操作的任意时段期间。

29. 发明授权

US07187573B2 Memory circuit and method of generating the same 有权
标题翻译：存储电路及其生成方法
公开(公告)号：US07187573B2
公开(公告)日：2007-03-06
申请号：US11011116
申请日：2004-12-15
申请人： Yutaka Terada , Hironori Akamatsu
发明人： Yutaka Terada , Hironori Akamatsu
IPC分类号： G11C5/06
CPC分类号： G11C7/1006 , G11C7/10 , G11C2207/104 , H01L27/10897
摘要： A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.
摘要翻译：存储电路10包括：馈通输入端13，用于在读取和写入存储单元时输入与要输入的信号不同的信号; 设置在存储单元布置的区域之间的中间缓冲电路14，用于中继通过馈通输入端13输入的信号; 以及用于输出由中间缓冲电路14中继的信号的馈通输出端子15。直通输入端子13和中间缓冲电路14之间以及中间缓冲电路14与馈通输出端子15之间的连接分别由馈通线16,17建立。当读取和布线存储单元或存储单元时，馈通线16,17不连接到要使用的导线。

30. 发明申请

US20050128818A1 Memory circuit and method of generating the same 有权
标题翻译：存储电路及其生成方法
公开(公告)号：US20050128818A1
公开(公告)日：2005-06-16
申请号：US11011116
申请日：2004-12-15
申请人： Yutaka Terada , Hironori Akamatsu
发明人： Yutaka Terada , Hironori Akamatsu
IPC分类号： G11C11/41 , G11C5/00 , G11C7/00 , G11C7/10 , G11C8/00 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： G11C7/1006 , G11C7/10 , G11C2207/104 , H01L27/10897
摘要： A memory circuit 10 includes: a feed-through input terminal 13 for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit 14 provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal 13; and a feed-through output terminal 15 for outputting the signal relayed by the intermediate buffer circuit 14. Connections between the feed-through input terminal 13 and the intermediate buffer circuit 14 and between the intermediate buffer circuit 14 and the feed-through output terminal 15 are established by feed-through wires 16, 17, respectively. The feed-through wires 16, 17 are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.
摘要翻译：存储电路10包括：馈通输入端13，用于在读取和写入存储单元时输入与要输入的信号不同的信号; 设置在存储单元布置的区域之间的中间缓冲电路14，用于中继通过馈通输入端13输入的信号; 以及用于输出由中间缓冲电路14中继的信号的馈通输出端子15。直通输入端子13和中间缓冲电路14之间以及中间缓冲电路14与馈通输出端子15之间的连接分别由馈通线16,17建立。当读取和布线存储单元或存储单元时，馈通线16,17不连接到要使用的导线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式