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21. 发明授权

US5824589A Method for forming bipolar transistor having a reduced base transit time 失效
标题翻译：具有降低的基本通行时间的形成双极晶体管的方法
公开(公告)号：US5824589A
公开(公告)日：1998-10-20
申请号：US915729
申请日：1997-08-21
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732
CPC分类号： H01L29/1004 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A bipolar transistor has a performance and high reliability, which are by enhancing a withstand voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, a first conductive film connected to the first diffusion layer, and an opening disposed in the first conductive film. A second impurity diffusion layer is formed in a portion, exposed from the opening portion, of the semiconducting substrate and is connected to the first impurity diffusion layer. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer is formed in the third impurity diffusion layer in the opening surrounded by the side walls.
摘要翻译：双极晶体管具有通过增强发射极和基极之间的耐受电压的性能和高可靠性。双极晶体管包括在半导体衬底中的第一杂质扩散层，连接到第一扩散层的第一导电膜和设置在第一导电膜中的开口。第二杂质扩散层形成在从半导体衬底的开口部露出的部分中，并连接到第一杂质扩散层。形成第三杂质扩散层以便容纳第二扩散层，并且在开口的侧壁上形成侧壁。在由侧壁包围的开口中的第三杂质扩散层中形成第四杂质扩散层。

22. 发明授权

US5629219A Method for making a complementary bipolar transistor 失效
标题翻译：制造互补双极晶体管的方法
公开(公告)号：US5629219A
公开(公告)日：1997-05-13
申请号：US520704
申请日：1995-08-29
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732 , H01L21/265
CPC分类号： H01L21/8228
摘要： A hole in the site for the emitter layer of the npn transistor of a complementary bipolar transistor is made in a step independent from a step of making a hole in the site for the emitter layer of the pnp transistor, and an n.sup.+ -type polycrystalline Si film doped with an n-type impurity upon being made is used to make the emitter electrode of the npn transistor. Independently from this step, a p.sup.+ -type polycrystalline Si film doped with a p-type impurity upon being made is used to make the emitter electrode of the pnp transistor. The n-type impurity diffusing from the emitter electrode makes an n.sup.+ -type emitter layer of the npn transistor, whereas the p-type impurity diffusing from the emitter electrode makes a p.sup.+ -type emitter layer of the pnp transistor. Thus the method can produce complementary bipolar transistors with a higher performance, and is suitable for combination with a process for fabricating sub-half-micron bipolar CMOSs.
摘要翻译：在互补双极晶体管的npn晶体管的发射极层的位置中的一个孔是独立于在pnp晶体管的发射极层的位置上形成空穴的步骤，并且n +型多晶Si 在制造时掺杂有n型杂质的薄膜用于制造npn晶体管的发射极。独立于该步骤，使用在制造时掺杂有p型杂质的p +型多晶Si膜来制造pnp晶体管的发射极。从发射电极扩散的n型杂质形成npn晶体管的n +型发射极层，而从发射极扩散的p型杂质形成pnp晶体管的p +型发射极层。因此，该方法可以产生具有更高性能的互补双极晶体管，并且适用于与用于制造亚半微米双极CMOS的工艺组合。

23. 发明授权

US5187554A Bipolar transistor 失效
标题翻译：双极晶体管
公开(公告)号：US5187554A
公开(公告)日：1993-02-16
申请号：US696301
申请日：1991-04-29
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/417 , H01L29/423
CPC分类号： H01L29/41708 , H01L29/42304
摘要： A bipolar transistor in which a buried collector region, a base region and an emitter region are formed in a device forming region surrounded by an isolation region and in which a base contact electrode and a collector contact electrode are arranged in symmetry with each other, and a process for preparing the transistor. The collector contact electrode is formed through an opening formed in a portion of the isolation region for connection with the buried collector region. In this manner, the collision between the base region and the collector contact region may be avoided effectively.
摘要翻译：一种双极晶体管，其中在由隔离区围绕的器件形成区域中形成掩埋的集电极区域，基极区域和发射极区域，并且其中基极接触电极和集电极接触电极彼此对称地布置，一种制备该晶体管的工艺。集电极接触电极通过形成在隔离区域的一部分中的开口形成，用于与埋设集电区连接。以这种方式，可以有效地避免基极区域和集电极接触区域之间的碰撞。

24. 发明授权

US06344384B2 Method of production of semiconductor device 失效
标题翻译：半导体器件的生产方法
公开(公告)号：US06344384B2
公开(公告)日：2002-02-05
申请号：US09859635
申请日：2001-05-18
申请人： Chihiro Arai , Hiroyuki Miwa
发明人： Chihiro Arai , Hiroyuki Miwa
IPC分类号： H01L218249
CPC分类号： H01L21/8249
摘要： A method of production of a semiconductor device able to be miniaturized by preventing the decline of the hfe at a low current caused by an increase of a surface recombination current of a bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in the BiCMOS process. An intrinsic base region of a first semiconductor element is formed, an insulating film having an opening at an emitter formation region of part of the intrinsic base region is formed, and then an emitter electrode of the first semiconductor element and a protective film are formed on an insulating film having the opening. Next, a sidewall insulating film is left on the gate electrode side portion. Simultaneously, the insulating film is removed while partially leaving the emitter region forming-use insulating film under the emitter electrode. Further, the external base region connected to the intrinsic base region is formed on the semiconductor substrate surface by self-alignment with respect to the emitter electrode.
摘要翻译：一种制造半导体器件的方法，该半导体器件能够通过防止双极型晶体管的表面复合电流的增加而引起的低电流引起的hfe的下降，并且通过相对于发射极的自对准来形成外部基极区域而能够小型化多晶硅在BiCMOS工艺中。形成第一半导体元件的本征基极区域，形成在本征基极部分的发射极形成区域具有开口的绝缘膜，然后在第一半导体元件的发射极电极和保护膜上形成保护膜具有开口的绝缘膜。接下来，在栅电极侧部分留下侧壁绝缘膜。同时，绝缘膜被去除，同时部分地将发射极区域形成用绝缘膜留在发射极电极下方。此外，通过相对于发射极电极的自对准，在半导体衬底表面上形成连接到本征基极区域的外部基极区域。

25. 发明授权

US06265276B1 Structure and fabrication of bipolar transistor 失效
标题翻译：双极晶体管的结构和制造
公开(公告)号：US06265276B1
公开(公告)日：2001-07-24
申请号：US09238703
申请日：1999-01-28
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L21331
CPC分类号： H01L21/82285 , H01L27/0826
摘要： A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor whereas the other doped polysilicon film is used for emitter of the NPN and a base of the PNP. The resulting base and emitter isolating structure is easy to fabricate, and self-aligned to the advantage of size reduction of individual devices.
摘要翻译：互补双极晶体管器件，由两个分离的导电膜制成，例如具有相反导电类型的两个高掺杂多晶硅膜。掺杂多晶硅膜用于NPN晶体管的基极和PNP晶体管的发射极，而另一个掺杂多晶硅膜用于NPN的发射极和PNP的基极。所得到的基极和发射极隔离结构易于制造，并且自对准以达到各个器件的尺寸减小的优点。

26. 发明授权

US6043554A Bipolar transistor and its manufacturing method 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US6043554A
公开(公告)日：2000-03-28
申请号：US788199
申请日：1997-01-24
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732 , H01L29/737 , H01L27/082
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/7322 , H01L29/7378
摘要： A p+ type graft base layer is formed both in a base layer of a p type epitaxial layer in a base opening of an insulating layer formed on a collector layer of an n type epitaxial layer and on an upper layer of the n type epitaxial layer contacting the p type epitaxial layer so that the graft base layer is positioned near the edge of the base opening, whereby a pn junction is formed away from the edge of the base opening where crystallinity of the p type epitaxial layer is deteriorated.
摘要翻译：在n型外延层的集电极层上形成的绝缘层的基部开口中的p型外延层的基极层和与n型外延层的n型外延层的上层接触的p +型接枝基层 p型外延层，使得接枝基底层位于基部开口的边缘附近，由此在p型外延层的结晶性劣化的同时形成离开基底开口的边缘的pn结。

27. 发明授权

US5352617A Method for manufacturing Bi-CMOS transistor devices 失效
标题翻译：制造Bi-CMOS晶体管器件的方法
公开(公告)号：US5352617A
公开(公告)日：1994-10-04
申请号：US51520
申请日：1993-04-26
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L21/8248 , H01L21/265
CPC分类号： H01L21/8248
摘要： A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor is disclosed, which comprises covering the bipolar transistor formation region with a gate insulating film and also with a first gate formation material at the time of the MOS transistor gate formation, removing the first gate formation material and gate insulating film covering at least a portion of the bipolar transistor formation region, thus forming an opening in the gate insulating film and first gate formation material, forming a second gate formation material, removing other portion of the first and second gate formation materials than on the bipolar transistor formation region and the MOS transistor gate formation region, forming an inter-layer insulating film, and removing the inter-layer insulating film and first and second gate formation materials on at least a portion of the bipolar transistor formation region, thus forming a second opening in the first-mentioned opening in the inter-layer insulating film and first and second gate formation materials.
摘要翻译：公开了一种制造具有双极晶体管和MOS晶体管的半导体器件的方法，其包括在MOS晶体管栅极形成时用栅极绝缘膜和第一栅极形成材料覆盖双极晶体管形成区域，去除所述第一栅极形成材料和栅极绝缘膜覆盖所述双极晶体管形成区域的至少一部分，从而在所述栅极绝缘膜和所述第一栅极形成材料中形成开口，形成第二栅极形成材料，去除所述第一和/ 第二栅极形成材料，而不是双极晶体管形成区域和MOS晶体管栅极形成区域，形成层间绝缘膜，并且在双极晶体的至少一部分上除去层间绝缘膜和第一和第二栅极形成材料晶体管形成区域，从而在第一开口中形成第二开口层间绝缘膜和第一和第二栅极形成材料。

28. 发明授权

US06808999B2 Method of making a bipolar transistor having a reduced base transit time 失效
标题翻译：制造具有降低的基础通行时间的双极晶体管的方法
公开(公告)号：US06808999B2
公开(公告)日：2004-10-26
申请号：US10055991
申请日：2002-01-28
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L29/1004
摘要： A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening disposed in the first conductive film. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer in the third impurity diffusion layer is formed in the opening surrounded by the side walls.
摘要翻译：双极晶体管具有通过增强发射极和基极之间的耐受电压而获得的高性能和高可靠性。双极晶体管包括在半导体衬底中的第一杂质扩散层，设置在第一导电膜中的开口。形成第三杂质扩散层以便容纳第二扩散层，并且在开口的侧壁上形成侧壁。在由侧壁包围的开口中形成第三杂质扩散层中的第四杂质扩散层。

29. 发明授权

US06323075B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06323075B1
公开(公告)日：2001-11-27
申请号：US09583279
申请日：2000-05-31
申请人： Hiroaki Ammo , Hiroyuki Miwa
发明人： Hiroaki Ammo , Hiroyuki Miwa
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： Disclosed is a method of fabricating a semiconductor device in which at least an LDD type insulated-gate field effect transistor and a bipolar transistor are formed on a common base substrate. An insulating layer for forming side walls of an LDD type insulated-gate field effect transistor is formed by a stack of first and second insulating films. An opening is formed in the lower first insulating film at a position in a bipolar transistor forming area, and a single crystal semiconductor layer is formed on a base substrate through the opening. With this configuration, the fabrication steps can be simplified and the reliability of the semiconductor device can be enhanced.
摘要翻译：公开了一种半导体器件的制造方法，其中在公共基底基板上形成至少一个LDD型绝缘栅场效应晶体管和双极晶体管。用于形成LDD型绝缘栅场效应晶体管的侧壁的绝缘层由第一和第二绝缘膜的叠层形成。在双极晶体管形成区域中的位置处，在下部第一绝缘膜中形成开口，并且通过该开口在基底基板上形成单晶半导体层。利用这种构造，可以简化制造步骤，并且可以提高半导体器件的可靠性。

30. 发明授权

US5955775A Structure of complementary bipolar transistors 失效
标题翻译：互补双极晶体管的结构
公开(公告)号：US5955775A
公开(公告)日：1999-09-21
申请号：US501634
申请日：1995-07-12
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732 , H01L29/00 , H01L27/102
CPC分类号： H01L21/82285 , H01L27/0826
摘要： A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor whereas the other doped polysilicon film is used for emitter of the NPN and a base of the PNP. The resulting base and emitter isolating structure is easy to fabricate, and self-aligned to the advantage of size reduction of individual devices.
摘要翻译：互补双极晶体管器件，由两个分离的导电膜制成，例如具有相反导电类型的两个高掺杂多晶硅膜。掺杂多晶硅膜用于NPN晶体管的基极和PNP晶体管的发射极，而另一个掺杂多晶硅膜用于NPN的发射极和PNP的基极。所得到的基极和发射极隔离结构易于制造，并且自对准以达到各个器件的尺寸减小的优点。

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