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21. 发明授权

US07203118B2 Semiconductor storage device and mobile electronic device 有权
标题翻译：半导体存储设备和移动电子设备
公开(公告)号：US07203118B2
公开(公告)日：2007-04-10
申请号：US10528997
申请日：2003-09-10
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Masaru Nawaki , Kei Tokui
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Masaru Nawaki , Kei Tokui
IPC分类号： G11C5/14
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7887
摘要： When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to a memory cell array 21 via the first switch SW1. When the input voltage determining circuit 24 determines that the input voltage is not higher than the prescribed voltage, the control circuit 25 turns off the first switch SW1 and turns on the second and third switches SW2 and SW3, thereby supplying a voltage from a charge pump 23 via the second and third switches SW2 and SW3. By this operation, the memory element is able to retain storage of two bits or more even if miniaturized, to execute stable operation with a small circuit area and to prevent circuit malfunction attributed to a small current supplied to the memory cell array.
摘要翻译：当输入电压确定电路24确定输入电压超过规定电压时，正极性功率选择电路22的控制电路25接通第一开关SW 1并关断第二和第三开关SW 2和SW 3，由此通过第一开关SW 1将输入电压提供给存储单元阵列21。当输入电压确定电路24确定输入电压不高于规定电压时，控制电路25关闭第一开关SW 1并接通第二和第三开关SW 2和SW 3，从而提供来自经由第二和第三开关SW 2和SW 3的电荷泵23。通过该操作，即使小型化，存储元件也能够保持两位以上的存储，能够以较小的电路面积进行稳定的动作，并且防止归因于提供给存储单元阵列的小电流引起的电路故障。

22. 发明授权

US07187588B2 Semiconductor storage 有权
标题翻译：半导体存储
公开(公告)号：US07187588B2
公开(公告)日：2007-03-06
申请号：US10506322
申请日：2003-03-03
申请人： Hiroshi Iwata , Akihide Shibata
发明人： Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C16/04
CPC分类号： H01L29/7923
摘要： A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two charge holding portions formed on both sides of the gate electrode, source/drain regions respectively corresponding to the charge holding portions, and a channel region disposed under the single gate electrode. A memory function implemented by these two charge holding portions and a transistor operation function implemented by the gate insulating film is separated from each other for securing sufficient memory function as well as easily suppressing short channel effect by making the gate insulating film thinner.
摘要翻译：半导体存储装置包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的单个栅电极，形成在栅电极两侧的两个电荷保持部分，分别对应于电荷保持部分和设置在单个栅电极下方的沟道区域。通过这两个电荷保持部分实现的存储功能和由栅极绝缘膜实现的晶体管操作功能彼此分离，以确保足够的存储功能，并且通过使栅极绝缘膜更薄来容易地抑制短沟道效应。

23. 发明申请

US20070014122A1 Lighting apparatus of vehicle door 失效
标题翻译：车门照明装置
公开(公告)号：US20070014122A1
公开(公告)日：2007-01-18
申请号：US11486046
申请日：2006-07-14
申请人： Koji Sakiyama , Hiroshi Iwata , Shigeru Yabuya , Takahiko Sato
发明人： Koji Sakiyama , Hiroshi Iwata , Shigeru Yabuya , Takahiko Sato
IPC分类号： B60Q1/26 , B60Q1/00
CPC分类号： B60Q1/323 , B60Q3/217 , B60Q3/64
摘要： An apparatus is provided that makes it possible to make following cars aware when a door is open and simultaneously illuminate a feet area, including, a lens that is attached at a door position that faces the feet area when a vehicle door is open, and a light guide member that is attached at a door position that faces following cars. One or more LEDs for the feet area are provided on the inner side of the lens, and one or more LEDs for the rear direction are provided that irradiate light on the light guide member.
摘要翻译：提供了一种装置，其使得可以在门打开时使下一个车辆知道，同时照亮脚区域，包括当车门打开时附接在面向脚区域的门位置处的镜片，以及导光构件，其安装在面向后续车辆的门位置。用于脚部区域的一个或多个LED设置在透镜的内侧，并且提供一个或多个用于向后方向的LED，其将光照射在导光构件上。

24. 发明授权

US07110297B2 Semiconductor storage device and mobile electronic apparatus 失效
标题翻译：半导体存储设备和移动电子设备
公开(公告)号：US07110297B2
公开(公告)日：2006-09-19
申请号：US10851733
申请日：2004-05-20
申请人： Yoshinao Morikawa , Masaru Nawaki , Hiroshi Iwata , Akihide Shibata
发明人： Yoshinao Morikawa , Masaru Nawaki , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C11/5671 , G11C16/0475 , G11C16/10 , H01L29/7923
摘要： A semiconductor storage device is provided, which comprises a memory array comprising memory elements. Each memory element comprises a gate electrode, a channel region, first and second diffusion regions, and first and second memory function sections provided an opposite aides of the gate electrode and having a function of retaining charges. The device further comprises a row decoder for selecting a word line in accordance with a row address, and a write control circuit for applying a write pulse to a bit line, which is connected to one of the first and second diffusion regions of the memory element connected to the selected word line, in accordance with a column address. The write control circuit controls the application of the write pulse so that a quantity of charges retained in one of the first and second memory function sections corresponds to a value of multibit data.
摘要翻译：提供一种半导体存储装置，其包括包括存储元件的存储器阵列。每个存储元件包括栅电极，沟道区，第一和第二扩散区，以及第一和第二存储功能部分，其设置有栅电极的相对侧并具有保持电荷的功能。该装置还包括用于根据行地址选择字线的行解码器和用于将写入脉冲施加到位线的写入控制电路，位线连接到存储元件的第一和第二扩散区域之一根据列地址连接到所选字线。写入控制电路控制写入脉冲的应用，使得保留在第一和第二存储器功能部分之一中的电荷量对应于多位数据的值。

25. 发明授权

US07079421B2 Method of improving data retention ability of semiconductor memory device, and semiconductor memory device 有权
标题翻译：提高半导体存储器件和半导体存储器件的数据保留能力的方法
公开(公告)号：US07079421B2
公开(公告)日：2006-07-18
申请号：US10848313
申请日：2004-05-19
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C11/34
CPC分类号： G11C16/102
摘要： This invention is a method of improving a data retention ability of a semiconductor memory device having a plurality of nonvolatile memory cells storing a plurality of memory states. The method includes the steps of: (a) selecting the nonvolatile memory cells in a first memory group each of which accumulates charges higher in level than a first threshold from the plurality of nonvolatile memory cells; (b) extracting the nonvolatile memory cells in a first sub-group each of which accumulates the charges lower in level than a second threshold from the nonvolatile memory cells in the first memory group; and (c) programming the nonvolatile memory cells in the first sub-group until each of the nonvolatile memory cells accumulates the charges higher in level than the second threshold.
摘要翻译：本发明是提高具有存储多个存储器状态的多个非易失性存储单元的半导体存储器件的数据保持能力的方法。该方法包括以下步骤：（a）选择第一存储器组中的非易失性存储单元，每个非易失性存储单元从多个非易失性存储器单元中累积比第一阈值高的电荷; （b）从第一存储器组中的非易失性存储单元中提取第一子组中的非易失性存储单元，每个非易失性存储单元累积低于第二阈值的电荷的电荷; 以及（c）对第一子组中的非易失性存储单元进行编程，直到每个非易失性存储单元累积高于第二阈值的电荷。

26. 发明申请

US20060131642A1 Semiconductor storage 有权
标题翻译：半导体存储
公开(公告)号：US20060131642A1
公开(公告)日：2006-06-22
申请号：US10530519
申请日：2003-10-01
申请人： Hiroshi Iwata , Akihide Shibata
发明人： Hiroshi Iwata , Akihide Shibata
IPC分类号： H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： In a semiconductor storage device, a gate insulating film (12) and a gate electrode (13) are laid on a first conductivity type semiconductor substrate (11), and charge holding portions (10A, 10B) are formed on both sides of the gate electrode (13). Second conductivity type first and second diffusion layer regions (17, 18) are formed in regions of the semiconductor substrate (11) corresponding to the charge holding portions (10A, 10B). The charge holding portions (10A, 10B) are each structured so as to change, in accordance with an electric charge amount held in the charge holding portions, a current amount flowing from one of the second conductivity type diffusion layer regions (17, 18) to the other of the diffusion layer regions through a channel region when voltage is applied to the gate electrode (13). Part of each charge holding portion (10A, 10B) is present below an interface of the gate insulating film (12) and the channel region.
摘要翻译：在半导体存储装置中，栅极绝缘膜（12）和栅电极（13）被放置在第一导电型半导体基板（11）上，电荷保持部（10A，10B）形成在栅电极（13）。第二导电类型的第一和第二扩散层区域（17,18）形成在对应于电荷保持部分（10A，10B）的半导体衬底（11）的区域中。电荷保持部（10A，10B）分别被构造成根据保持在电荷保持部中的电荷量来改变从第二导电型扩散层区域（17， 18），当电压施加到栅电极（13）时，通过沟道区域到另一个扩散层区域。每个电荷保持部分（10A，10B）的一部分存在于栅极绝缘膜（12）和沟道区域的界面之下。

27. 发明授权

US07061808B2 Semiconductor memory device, driving method thereof, and portable electronic apparatus 失效
标题翻译：半导体存储器件，其驱动方法和便携式电子设备
公开(公告)号：US07061808B2
公开(公告)日：2006-06-13
申请号：US10847627
申请日：2004-05-18
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C16/04
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/3454 , G11C16/3459 , H01L21/28282 , H01L29/42332 , H01L29/7887
摘要： A semiconductor memory device includes a memory array; a storage section that receives a maximum pulse value from a user of the semiconductor memory device; a control section that executes a writing processing or an erasing processing for the memory array and restarts the writing or erasing processing in the case where the processing for the memory array has failed; a counter section that counts up a number of processings performed by the control section; and a detection section that detects when the number of processings is equal to the maximum pulse value to prevent the control section from restarting the writing or erasing processing.
摘要翻译：半导体存储器件包括存储器阵列; 存储部，其从半导体存储器件的用户接收最大脉冲值; 在存储器阵列的处理失败的情况下执行对存储器阵列的写入处理或擦除处理并重新开始写入或擦除处理的控制部分; 对由所述控制部执行的处理次数进行计数的计数部; 以及检测部，其检测处理次数等于最大脉冲值，以防止控制部重新开始写入或擦除处理。

28. 发明授权

US07053437B2 Semiconductor memory device, semiconductor device and methods of manufacturing them, portable electronic equipment, and IC card 有权
标题翻译：半导体存储器件，半导体器件及其制造方法，便携式电子设备和IC卡
公开(公告)号：US07053437B2
公开(公告)日：2006-05-30
申请号：US10848214
申请日：2004-05-19
申请人： Hiroshi Iwata , Takayuki Ogura , Akihide Shibata
发明人： Hiroshi Iwata , Takayuki Ogura , Akihide Shibata
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： A semiconductor memory device including memory cells, each memory cell including: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region located below the gate electrode; a pair of source and drain regions arranged on a opposite sides, respectively, of the channel region, the source and drain regions having a conductive type opposite to that of the channel region; and memory functional units located on opposite sides, respectively, of the gate electrode, each memory functional unit including a charge retaining portion and an anti-dissipation insulator, the charge retaining portion being made of a material serving to store charges, the anti-dissipation insulator serving to prevent the stored charges from being dissipated by separating the charge retaining portion from both the gate electrode and the substrate, wherein a distance between a side wall of the gate electrode and a side of the charge retaining portion facing each other (T2) is adapted to differ from a distance between a bottom of the charge retaining portion and a surface of the substrate (T1).
摘要翻译：一种包括存储单元的半导体存储器件，每个存储单元包括：形成在半导体衬底上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 位于栅电极下方的沟道区; 一对源极和漏极区分别布置在沟道区的相对侧上，源极和漏极区具有与沟道区相反的导电类型; 以及分别位于栅电极的相对侧的存储功能单元，每个存储功能单元包括电荷保持部分和消耗绝缘体，电荷保持部分由用于存储电荷的材料制成，抗耗散绝缘体，用于通过将电荷保持部分与栅极电极和衬底分离来防止存储的电荷消散，其中栅电极的侧壁和电荷保持部分的面彼此相对的距离（T 2 ）适于不同于电荷保持部分的底部和基板（T 1）的表面之间的距离。

29. 发明申请

US20060109729A1 Semiconductor storage device and mobile electronic device 有权
标题翻译：半导体存储设备和移动电子设备
公开(公告)号：US20060109729A1
公开(公告)日：2006-05-25
申请号：US10528997
申请日：2003-09-10
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Masaru Nawaki , Kei Tokui
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Masaru Nawaki , Kei Tokui
IPC分类号： G11C5/14
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7887
摘要： When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to a memory cell array 21 via the first switch SW1. When the input voltage determining circuit 24 determines that the input voltage is not higher than the prescribed voltage, the control circuit 25 turns off the first switch SW1 and turns on the second and third switches SW2 and SW3, thereby supplying a voltage from a charge pump 23 via the second and third switches SW2 and SW3. By this operation, the memory element is able to retain storage of two bits or more even if miniaturized, to execute stable operation with a small circuit area and to prevent circuit malfunction attributed to a small current supplied to the memory cell array.
摘要翻译：当输入电压确定电路24确定输入电压超过规定电压时，正极性功率选择电路22的控制电路25接通第一开关SW 1并关断第二和第三开关SW 2和SW 3，由此通过第一开关SW 1将输入电压提供给存储单元阵列21。当输入电压确定电路24确定输入电压不高于规定电压时，控制电路25关断第一开关SW 1并接通第二和第三开关SW 2和SW 3，从而提供来自经由第二和第三开关SW 2和SW 3的电荷泵23。通过该操作，即使小型化，存储元件也能够保持两位以上的存储，能够以较小的电路面积进行稳定的动作，并且防止归因于提供给存储单元阵列的小电流引起的电路故障。

30. 发明授权

US07009892B2 Semiconductor memory device and portable electronic apparatus 失效
标题翻译：半导体存储器件和便携式电子设备
公开(公告)号：US07009892B2
公开(公告)日：2006-03-07
申请号：US10850896
申请日：2004-05-20
申请人： Yoshinao Morikawa , Masaru Nawaki , Hiroshi Iwata , Akihide Shibata
发明人： Yoshinao Morikawa , Masaru Nawaki , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C7/00
CPC分类号： H01L29/66833 , G11C7/22 , G11C16/0475 , G11C16/0491 , G11C16/10 , H01L21/28282 , H01L29/7923
摘要： A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for writing from a plurality of planes in which memory cells are arranged in an array, an address selection circuit disposed for each of the planes, and an address buffer circuit for simultaneously providing a write address and a read address. Each of the address selection circuits is configured so as to be able to receive one of the read selection signals and one of the write selection signals from the control logic circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.
摘要翻译：一种半导体存储器件，包括用于产生读取选择信号的控制逻辑电路，每个读取选择信号选择一个平面用于读取和写入选择信号，每个选择信号从阵列中排列存储器单元的多个平面中选择一个写入平面，地址选择电路设置以及用于同时提供写入地址和读取地址的地址缓冲器电路。每个地址选择电路被配置为能够从控制逻辑电路接收读取选择信号中的一个和写入选择信号中的一个。存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧并具有与沟道区域相反的导电类型的扩散区域，以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元。

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