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1. 发明授权

US07405974B2 Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device 有权
标题翻译：半导体存储器件，页缓冲器资源分配方法及其电路，计算机系统和移动电子设备
公开(公告)号：US07405974B2
公开(公告)日：2008-07-29
申请号：US10848324
申请日：2004-05-19
申请人： Yoshifumi Yaoi , Yasuaki Iwase , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yoshifumi Yaoi , Yasuaki Iwase , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C7/10 , G11C7/1039 , G11C2207/2245
摘要： A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.
摘要翻译：半导体存储器件包括页缓冲电路和存储元件的布置，每个存储元件包括：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极两侧的具有存储电荷功能的记忆功能部件。页面缓冲电路提供了在存储器阵列控制器和用户之间共享的公共资源。页面缓冲电路具有包含随机存取存储器阵列的两个平面。页面缓冲电路还包括模式控制部分，以便以用户模式访问主总线上的平面并且以存储器控制模式通过存储器阵列控制器访问平面。

2. 发明申请

US20070097762A1 Semiconductor storage device, redundancy circuit thereof, and portable electronic device 审中-公开
公开(公告)号：US20070097762A1
公开(公告)日：2007-05-03
申请号：US11641739
申请日：2006-12-20
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C29/00
CPC分类号： G11C29/838 , G11C16/0475 , G11C16/22 , G11C29/785 , G11C29/787 , G11C29/789 , H01L29/42332 , H01L29/7887 , H01L29/7923
摘要： A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit addresses a single chip memory including cells associated with a plurality of redundant lines and includes a decoder for selecting a redundant row. The semiconductor storage device can permanently inactivate further programming of the redundancy circuit in order to prevent a user from performing inadvertent programming.

3. 发明授权

US07116579B2 Semiconductor storage device and mobile electronic apparatus 失效
标题翻译：半导体存储设备和移动电子设备
公开(公告)号：US07116579B2
公开(公告)日：2006-10-03
申请号：US10851517
申请日：2004-05-20
申请人： Yoshinao Morikawa , Masaru Nawaki , Hiroshi Iwata , Akihide Shibata
发明人： Yoshinao Morikawa , Masaru Nawaki , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect to the memory array, a decoder for decoding a signal indicating a current state of the write state machine, which is output from the write state machine, and outputting a status signal indicating a status of the program or erase operation with respect to the memory array, a status register for storing the status signal, and an output circuit for outputting the status signal stored in the status register. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.
摘要翻译：提供了一种半导体存储装置，其包括存储器阵列，其包括存储器元件，用于执行关于存储器阵列的编程或擦除操作序列的写入状态机，用于对指示写入的当前状态的信号进行解码的解码器状态机，其从写入状态机输出，并且输出指示关于存储器阵列的编程或擦除操作的状态的状态信号，用于存储状态信号的状态寄存器，以及用于输出状态的输出电路信号存储在状态寄存器中。每个存储元件包括栅电极，沟道区，扩散区和设置在栅电极的相对侧上并具有保持电荷的功能的存储功能部。

4. 发明授权

US06982906B2 Electrically programmable and electrically erasable semiconductor memory device 失效
标题翻译：电可编程和电可擦除半导体存储器件
公开(公告)号：US06982906B2
公开(公告)日：2006-01-03
申请号：US10841688
申请日：2004-05-06
申请人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
发明人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C16/06
CPC分类号： H01L29/7923 , G11C16/3454 , H01L21/28282
摘要： A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell. It is thereby possible to improve the speed of writing and erasing processes on a nonvolatile memory cell of the present invention and to improve reliability.
摘要翻译：本发明的半导体存储器件包括电可编程和可擦除的非易失性存储器件，其使用需要第一电位读取数据的多个存储器单元和用于数据编程的第二电位，第二电位高于第一电位，a 锁存电路，用于接收数据和临时存储数据;脉冲发生器，其生成用于将数据编程到存储器单元中并被耦合以便接收第二电位的脉冲;比较器，用于将锁存电路中的数据与存储单元和控制器，用于控制脉冲发生器重复产生脉冲，直到锁存电路中的数据与存储单元中的数据匹配，该控制器耦合到比较器和脉冲发生器。控制器控制，使脉冲重复生成，直到数据被编程到存储单元中。由此，能够提高本发明的非易失性存储单元的写入和擦除处理速度，提高可靠性。

5. 发明授权

US06894929B2 Method of programming semiconductor memory device having memory cells and method of erasing the same 失效
标题翻译：具有存储单元的半导体存储器件的编程方法及其擦除方法
公开(公告)号：US06894929B2
公开(公告)日：2005-05-17
申请号：US10843149
申请日：2004-05-10
申请人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
发明人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3468
摘要： The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the programming level to the memory cell with the flag.
摘要翻译：本发明提供了一种对计算机编程具有多个存储单元的存储器阵列的方法，所述存储器阵列包括验证步骤1，该验证步骤1验证存储器单元是否已被编程，或者每个存储器单元尚未被编程在存储单元受此之后验证存储单元尚未被编程的几个验证步骤的情况下，标记存储单元的标记步骤2，即使确认存储器单元已经被编程，第一应用步骤3，将没有任何标志的具有编程级别的编程脉冲施加到未编程的存储器单元;重复步骤4，重复验证步骤1，标记步骤2和第一应用步骤3，直到验证所有存储器单元已经被编程至少一次，以及施加具有升压编程电平的升压脉冲的第二应用步骤5 比编程级别低到具有标志的存储单元。

6. 发明申请

US20050041472A1 Semiconductor memory device and portable electronic apparatus 失效
标题翻译：半导体存储器件和便携式电子设备
公开(公告)号：US20050041472A1
公开(公告)日：2005-02-24
申请号：US10851709
申请日：2004-05-20
申请人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
发明人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C16/04 , G11C16/02 , G11C16/08 , G11C16/10 , G11C16/16 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/10 , G11C16/16 , H01L21/28282 , H01L29/7923
摘要： The present invention provides a semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, a user interface circuit including a command queue having a logic circuit for accepting commands issued by an external user and generating a program memory address, and an array control circuit having a microcontroller and a program memory for storing therein an execution code, and executing an operation on the memory cell array, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
摘要翻译：本发明提供了一种半导体存储器件，包括其中布置有多个存储器单元的存储单元阵列，用户接口电路包括具有用于接受由外部用户发出的命令并产生程序存储器地址的逻辑电路的命令队列，以及阵列控制电路，具有微控制器和程序存储器，用于在其中存储执行代码，并对存储单元阵列执行操作，其中存储单元包括通过栅极绝缘膜形成在半导体层上的栅电极，设置在栅极电极下方的扩散区域，设置在沟道区域的两侧并具有与沟道区域相反的导电类型的扩散区域，以及形成在栅电极两侧并具有保持电荷功能的存储功能元件。

7. 发明申请

US20050001243A1 Semiconductor storage device, display device and portable electronic equipment 失效
标题翻译：半导体存储设备，显示设备和便携式电子设备
公开(公告)号：US20050001243A1
公开(公告)日：2005-01-06
申请号：US10848260
申请日：2004-05-19
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/34 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792 , H01L31/062
CPC分类号： H01L29/66833 , G11C11/5628 , G11C16/0475 , G11C16/0491 , G11C16/3454 , H01L21/28282 , H01L29/792
摘要： A semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements are arranged and a program verify circuit 30. The memory element 1, 33 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on opposite sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies 109 that are located on opposite sides of the gate electrode 104 and have a function of retaining electric charge. A program load register 32 of the program verify circuit 30 eliminates a state that a memory element 33 which has initially been verified as having been correctly programmed needs to be further programmed.
摘要翻译：半导体存储装置包括其中布置有多个存储元件的存储单元阵列21和编程验证电路30.存储元件1,33包括通过栅极绝缘体103形成在半导体层102上的栅电极104，沟道区域布置在栅电极104的下方，扩散区域107a，107b位于沟道区域的相对侧并具有与沟道区域相反的导电类型，以及存储器功能体109，其位于栅电极104，具有保持电荷的功能。程序验证电路30的程序加载寄存器32消除了最初被验证为被正确编程的存储元件33需要被进一步编程的状态。

8. 发明授权

US07167402B2 Semiconductor storage device, redundancy circuit thereof, and portable electronic device 有权
标题翻译：半导体存储装置，其冗余电路和便携式电子装置
公开(公告)号：US07167402B2
公开(公告)日：2007-01-23
申请号：US10848481
申请日：2004-05-19
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C29/00 , G11C11/34
CPC分类号： G11C29/838 , G11C16/0475 , G11C16/22 , G11C29/785 , G11C29/787 , G11C29/789 , H01L29/42332 , H01L29/7887 , H01L29/7923
摘要： A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit addresses a single chip memory including cells associated with a plurality of redundant lines and includes a decoder for selecting a redundant row. The semiconductor storage device can permanently inactivate further programming of the redundancy circuit in order to prevent a user from performing inadvertent programming.
摘要翻译：半导体存储装置包括多个存储元件和冗余电路。每个存储元件包括设置在半导体层上的栅极电极，介于栅电极和半导体层之间的栅极绝缘膜，设置在栅电极下方的沟道区，分别设置在沟道区两侧的扩散区，具有与沟道区的导电类型相反的导电类型的扩散区和分别设置在栅极两侧的存储功能元件，存储功能元件具有保持电荷的功能。冗余电路解决包括与多条冗余线相关联的单元的单个芯片存储器，并且包括用于选择冗余行的解码器。半导体存储设备可以永久地停用冗余电路的进一步编程，以防止用户执行无意编程。

9. 发明授权

US07161207B2 Computer system, memory structure and structure for providing storage of data 失效
标题翻译：计算机系统，存储器结构和结构，用于提供数据存储
公开(公告)号：US07161207B2
公开(公告)日：2007-01-09
申请号：US10840173
申请日：2004-05-05
申请人： Koji Hamaguchi , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
发明人： Koji Hamaguchi , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
IPC分类号： H01L29/79
CPC分类号： H01L29/66833 , G11C16/10 , G11C16/30 , H01L21/28282 , H01L29/7923
摘要： A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.
摘要翻译：一种计算机系统，包括：（A）CPU; （B）存储装置，包括：（i）包括多个侧壁存储晶体管的侧壁存储器阵列; （ii）电荷泵; （iii）多个开关电路; 和（iv）逻辑电路; 和（C）系统总线，其中每个侧壁存储晶体管包括：形成在半导体层上的栅电极，其上形成有在半导体层上的栅极绝缘膜; 形成在栅电极下方的沟道区; 一对扩散区，形成在沟道区的两侧，具有与沟道区相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的一对记忆功能单元。

10. 发明授权

US07092295B2 Semiconductor memory device and portable electronic apparatus including the same 有权
标题翻译：半导体存储器件和包括其的便携式电子设备
公开(公告)号：US07092295B2
公开(公告)日：2006-08-15
申请号：US10847626
申请日：2004-05-18
申请人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C16/04
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50 , G11C2029/0403 , G11C2029/5002
摘要： A semiconductor memory device includes a controller programming a nonvolatile memory cell by applying a first pulse so that a charge amount smaller than a target charge amount is accumulated in the nonvolatile memory cell, a second pulse train so that a second charge amount smaller than the target charge amount and larger than the first charge amount is accumulated in the nonvolatile memory cell, and a third pulse train so that a third charge amount falling within an allowable error range of the target charge amount is accumulated. The semiconductor memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and memory functional units formed on both sides of the gate electrode.
摘要翻译：一种半导体存储器件包括：控制器，通过施加第一脉冲来编程非易失性存储器单元，使得小于目标电荷量的电荷量累积在非易失性存储单元中，第二脉冲串使得小于目标的第二电荷量充电量大于第一充电量的电荷量累积在非易失性存储单元中，并且第三脉冲串使得落入目标充电量的容许误差范围内的第三充电量被累积。半导体存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅电极下方的沟道区域，设置在沟道区域两侧的扩散区域和形成在栅电极两侧的存储功能单元。

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