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21. 发明授权

US08841701B2 FinFET device having a channel defined in a diamond-like shape semiconductor structure 有权
标题翻译：具有限定在菱形半导体结构中的沟道的FinFET器件
公开(公告)号：US08841701B2
公开(公告)日：2014-09-23
申请号：US13220979
申请日：2011-08-30
申请人： You-Ru Lin , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： You-Ru Lin , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/66 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/02609 , H01L21/30604 , H01L21/76224 , H01L29/045 , H01L29/0649 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/7853
摘要： The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
摘要翻译：本公开提供了一种FinFET器件。 FinFET器件包括第一半导体材料的半导体衬底; 覆盖半导体衬底的第一半导体材料的鳍结构，其中鳍结构具有第一晶面取向的顶表面; 设置在所述翅片结构的顶表面上的第二半导体材料的菱形形状结构，其中所述菱形形状结构具有至少一个第二晶面取向的表面; 设置在所述菱形形状结构上的栅极结构，其中所述栅极结构分离源极区域和漏极区域; 以及在源极和漏极区域之间以菱形形状结构限定的沟道区域。

22. 发明授权

US08836016B2 Semiconductor structures and methods with high mobility and high energy bandgap materials 有权
标题翻译：具有高迁移率和高能带隙材料的半导体结构和方法
公开(公告)号：US08836016B2
公开(公告)日：2014-09-16
申请号：US13415339
申请日：2012-03-08
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/772
CPC分类号： H01L29/7851 , H01L21/0259 , H01L21/02636 , H01L21/02639 , H01L21/02658 , H01L21/76224 , H01L21/8252 , H01L29/0649 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/267 , H01L29/66462 , H01L29/66522 , H01L29/66795 , H01L29/7786 , H01L29/7842 , H01L29/7848 , H01L29/785
摘要： An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
摘要翻译：实施例是包括基板，高能带隙材料和高载流子迁移率材料的结构。衬底包括第一隔离区域和第二隔离区域。第一隔离区域和第二隔离区域中的每一个在第一和第二隔离区域之间延伸到衬底的第一表面的下方。高能带隙材料在衬底的第一表面上方并且设置在第一和第二隔离区之间。高载流子迁移率材料超过高能带隙材料。高载流子迁移率材料比第一和第二隔离区域的相应顶表面高，以形成翅片。

23. 发明申请

US20130248948A1 Source/Drain Profile for FinFET 有权
公开(公告)号：US20130248948A1
公开(公告)日：2013-09-26
申请号：US13426106
申请日：2012-03-21
申请人： Ta-Chun Ma , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Ta-Chun Ma , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02639 , H01L21/30604 , H01L21/3083 , H01L29/045 , H01L29/0688 , H01L29/1037 , H01L29/66636 , H01L29/66681 , H01L29/66795 , H01L29/7816 , H01L29/7833 , H01L29/7851 , H01L29/7853
摘要： An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.

24. 发明申请

US20130168771A1 Method of Forming CMOS FinFET Device 有权
标题翻译： CMOS FinFET器件的形成方法
公开(公告)号：US20130168771A1
公开(公告)日：2013-07-04
申请号：US13340937
申请日：2011-12-30
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L27/12 , H01L21/84 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/1211 , H01L21/823821 , H01L21/8258 , H01L21/845 , H01L29/1054 , H01L29/267
摘要： A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.
摘要翻译：公开了一种用于制造CMOS FinFET器件的CMOS FinFET器件和方法。示例性的CMOS FinFET器件包括包括第一区域和第二区域的衬底。 CMOS FinFET还包括布置在衬底上的翅片结构，其包括在第一区域中的第一鳍片和在第二区域中的第二鳍片。 CMOS FinFET还包括第一鳍片的第一部分，其包括与衬底相同的材料的材料，以及第一鳍片的第二部分，其包括沉积在第一鳍片的第一部分上的III-V半导体材料。 CMOS FinFET还包括第二鳍片的第一部分，其包括与衬底相同的材料，第二鳍片的第二部分包括沉积在第二鳍片的第一部分上的锗（Ge）材料。

25. 发明授权

US09601594B2 Semiconductor device with enhanced strain 有权
公开(公告)号：US09601594B2
公开(公告)日：2017-03-21
申请号：US13295178
申请日：2011-11-14
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/70 , H01L21/76 , H01L29/66 , H01L29/78 , H01L29/08 , H01L21/762
CPC分类号： H01L29/0847 , H01L21/76224 , H01L29/66575 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

26. 发明授权

US08815712B2 Method for epitaxial re-growth of semiconductor region 有权
标题翻译：半导体区域的外延再生长方法
公开(公告)号：US08815712B2
公开(公告)日：2014-08-26
申请号：US13414357
申请日：2012-03-07
申请人： Cheng-Tien Wan , You-Ru Lin , Yi-Jing Lee , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Tien Wan , You-Ru Lin , Yi-Jing Lee , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L21/3065 , H01L21/02057 , H01L21/02381 , H01L21/02532 , H01L21/02538 , H01L21/02658 , H01L29/66636 , H01L29/78
摘要： A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
摘要翻译：在第一半导体区域的表面上进行处理，其中使用包括含氧气体和用于蚀刻半导体材料的蚀刻气体的处理气体进行处理。进行外延以在第一半导体区域的表面上生长第二半导体区域。

27. 发明授权

US08759203B2 Growing III-V compound semiconductors from trenches filled with intermediate layers 有权
标题翻译：从填充有中间层的沟槽中生长III-V族化合物半导体
公开(公告)号：US08759203B2
公开(公告)日：2014-06-24
申请号：US12842221
申请日：2010-07-23
申请人： Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
发明人： Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
IPC分类号： H01L21/20
CPC分类号： H01L21/02647 , H01L21/02381 , H01L21/02389 , H01L21/02458 , H01L21/02463 , H01L21/0254 , H01L21/02546 , H01L21/02617 , H01L21/02639
摘要： A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
摘要翻译：形成集成电路结构的方法包括在衬底的至少一部分上形成绝缘层; 在所述绝缘层的顶表面上形成多个半导体柱。多个半导体柱由绝缘层的一部分水平隔开。以周期性图案分配多个半导体柱。该方法还包括从半导体柱的顶表面和侧壁外延生长III-V族化合物半导体膜。

28. 发明申请

US20130171792A1 Methods for Semiconductor Regrowth 有权
标题翻译：半导体再生方法
公开(公告)号：US20130171792A1
公开(公告)日：2013-07-04
申请号：US13414357
申请日：2012-03-07
申请人： Cheng-Tien Wan , You-Ru Lin , Yi-Jing Lee , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Tien Wan , You-Ru Lin , Yi-Jing Lee , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/762 , H01L21/336
CPC分类号： H01L21/3065 , H01L21/02057 , H01L21/02381 , H01L21/02532 , H01L21/02538 , H01L21/02658 , H01L29/66636 , H01L29/78
摘要： A treatment is performed on a surface of a first semiconductor region, wherein the treatment is performed using process gases including an oxygen-containing gas and an etching gas for etching the semiconductor material. An epitaxy is performed to grow a second semiconductor region on the surface of the first semiconductor region.
摘要翻译：在第一半导体区域的表面上进行处理，其中使用包括含氧气体和用于蚀刻半导体材料的蚀刻气体的处理气体进行处理。进行外延以在第一半导体区域的表面上生长第二半导体区域。

29. 发明授权

US08183134B2 Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces 有权
标题翻译：具有提高硅表面III-V化合物外延质量的半导体器件和制造方法
公开(公告)号：US08183134B2
公开(公告)日：2012-05-22
申请号：US13009151
申请日：2011-01-19
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/02667 , H01L21/02675
摘要： Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.
摘要翻译：通过在沟槽中外延生长III-V族化合物半导体区域，然后对该区域进行封盖和退火来减少或消除堆叠故障。封盖层限制了原子从该区域的逃逸，并且能够与退火一起减少或消除堆垛层错。

30. 发明申请

US20120025201A1 Inverted Trapezoidal Recess for Epitaxial Growth 有权
标题翻译：反向梯形凹槽用于外延生长
公开(公告)号：US20120025201A1
公开(公告)日：2012-02-02
申请号：US12847877
申请日：2010-07-30
申请人： Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
发明人： Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/76283 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/31111 , H01L21/32055 , H01L21/76224 , H01L21/76272 , H01L29/045 , H01L29/0657 , H01L29/0692 , H01L29/2003
摘要： A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.
摘要翻译：提供具有外延层的半导体器件的制造方法。半导体器件具有形成在其中的沟槽的衬底和形成在沟槽下方的凹部。凹槽具有（111）晶体取向的侧壁。沟槽的深度使得深度大于或等于凹部的侧壁长度的二分之一。在凹槽和沟槽中形成外延层。沟槽的深度足以引起在半导体衬底和外延层的界面之间形成的位错，从而沿沟槽的侧壁终止。

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